Deserializer Rx Clock Delay for Parallel Bus Data Alignment
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Solution Overview
Problem
In high-speed serializer-deserializer (HSS) cores, the repeated clock signal at the end of the clock tree experiences substantial delay, leading to misalignment with the original clock signal, causing data invalidity when read by devices, and existing solutions require additional cells and manual intervention, increasing latency.
Innovation Solution
A clock delay unit is introduced to align the end point clock signal with the deserialization clock, eliminating the need for parallel data delay and simplifying timing analysis by ensuring each data unit is valid when the repeated clock pulse is asserted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock tree with repeaters is used to distribute the clock signal, then the clock signal can reach all devices, but substantial delay is propagated through the system
Solution Approach 1:
The patent applies preliminary action by delaying the parallel data signals in advance to match the clock tree delay. The delay unit introduces a delay equal to the clock tree delay to the parallel data bus, so that when the delayed clock signal arrives at the sampling device, the data is already aligned and ready for valid sampling. This pre-synchronization eliminates the timing mismatch problem.
2Reliability
If delay is added to parallel data to match clock tree delay, then data alignment is achieved, but extra cells are needed and manual intervention is required
Solution Approach 1:
The patent merges the delay function into the existing clock tree structure by placing delay units within the clock distribution network itself. Instead of adding separate delay cells for each data path, the delay is integrated into the clock signal path, allowing a single delay unit to synchronize the entire parallel bus with the clock tree, thereby reducing overall device complexity.
3Reliability
If delay is added to parallel data to match clock tree delay, then data alignment is achieved, but overall latency of the interface increases
Solution Approach 1:
The patent applies local quality by introducing delay only where necessary - specifically in the data paths that require synchronization with the clock tree - rather than adding uniform delay to all signals. The delay units are strategically placed only in the parallel data bus paths, leaving other critical paths unaffected, thus minimizing overall interface latency while achieving the necessary alignment.
4Productivity
If the sampling device reads data on the leading edge of the delayed clock signal, then data can be read, but the data is not valid when the leading edge is asserted
Solution Approach 1:
The patent applies preliminary action by pre-delaying the parallel data signals through delay units matched to the clock tree delay. This ensures that when the delayed clock signal reaches the sampling device, the data signals have already been held in sync, so the leading edge of the clock now coincides with valid data on the parallel bus, enabling correct sampling without timing errors.
Data Source
AI summary
In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.