Deserializer Bit Shifting with Strobe Mux for High-Speed Capture
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Solution Overview
Problem
Conventional deserializers face challenges in scaling with increasing input data speed, leading to slower overall circuit performance due to larger muxing and increased loading on register outputs, making them impractical for small, low-cost integrated circuit devices like FPGAs.
Innovation Solution
A method and apparatus that utilize a strobe mux with a single multiplexer and delayed clock signals to control the order of bit capture in an intermediate register bank, allowing for scalable bit shifting without compromising operating speed, and enabling the transfer of high-speed data to a low-speed clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the deserializer width is increased to handle faster input data, then the input data speed is improved, but the overall circuit speed decreases due to larger muxing and increased loading on register outputs
Solution Approach 1:
The patent divides the deserializer into multiple smaller deserializers, each handling a portion of the input data. Instead of using one large deserializer with wide register banks and complex muxing, the system uses several narrow deserializers that can operate in parallel or sequentially, maintaining faster clock speeds while achieving the same overall throughput
Solution Approach 2:
The patent transitions from a single-wide deserializer architecture to a multi-narrow-deserializer architecture, effectively adding a dimension of parallelism. This allows the system to maintain high operating frequencies by avoiding the speed penalties of wide muxing and large register banks
2Quantity of substance
If the number of bits in the register banks is increased to handle wider data words, then the data word width is improved, but the circuit delay increases making the deserializer impractical for small IC devices
Solution Approach 1:
The patent segments the wide data word handling across multiple smaller deserializers, each with narrower register banks. This avoids the need for large, slow register banks in a single deserializer while still achieving the required data word width through parallel or sequential processing of the segmented data
Solution Approach 2:
The patent combines the outputs of multiple smaller deserializers to achieve the equivalent functionality of a single wide deserializer. By merging the results from several narrow deserializers, the system achieves wide data word handling without the circuit delay penalties of a single large deserializer
Data Source
AI summary
In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.