Design Rule Checking System for Semiconductor Yield Optimization
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Solution Overview
Problem
As semiconductor device sizes shrink and design rule sets become increasingly complex, extensive time is spent on design rule checking and manual examination of design rules, leading to inefficiencies in the semiconductor manufacturing process.
Innovation Solution
A method is introduced that involves performing first and reverse design rule checks, analyzing violations, determining rule usage rates, and forming a rule database to identify and replace minimum rules with standard rules, thereby improving the pass/fail yield rate and reducing the number of minimum design rules used in the layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design rule sets become increasingly complex to accommodate smaller device sizes, then manufacturing precision is improved, but design rule checking time and process complexity increase
Solution Approach 1:
The patent changes the parameter of rule strictness by introducing minimum rules as an optional filtering mechanism. Instead of applying all design rules uniformly, the system allows selective application of rules based on their strictness level, thereby reducing checking time while maintaining necessary precision for critical dimensions
Solution Approach 2:
The patent segments the design rule set into different categories (standard rules and minimum rules) with different enforcement levels. This segmentation allows the system to process rules in prioritized stages, checking critical minimum rules first and optionally checking standard rules, thus reducing overall checking time while preserving manufacturing precision for essential parameters
2Manufacturing precision
If design rule sets become increasingly complex, then manufacturing precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent implements self-service by enabling the DRC system to automatically identify and report minimum rule violations without requiring manual intervention. The system autonomously performs rule checking, generates violation reports, and provides actionable feedback, thereby maintaining high manufacturing precision while significantly improving ease of operation by eliminating manual examination requirements
Solution Approach 2:
The patent introduces feedback mechanisms where the system automatically generates and reports design rule violations, providing real-time information about minimum rule breaches. This feedback loop enables designers to quickly identify and correct issues without manual checking, maintaining precision while improving operational ease through automated information provision
3Reliability
If minimum design rules are used to ensure sufficient margins, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by differentiating between minimum rules and standard rules, applying minimum rules only where necessary to ensure sufficient margins for reliability, while allowing standard rules to be applied selectively. This localized application of strictness maintains reliability for critical dimensions while reducing overall device complexity by not uniformly applying all design rules across the entire layout
Data Source
AI summary
A target integrated circuit layout having a plurality of design rules having minimum rules and standard rules used in the target integrated circuit layout is provided. First and second design rule checks are performed, where respective first and second sets of violations of the plurality of design rules and each design rule associated with the first and second sets of violations are recorded. An analysis is performed on the first and second sets of violations, each design rule associated with the first and second sets of violations, and a frequency of usage of each of the plurality of design rules, and a rule usage rate is determined having a number of minimum rules used overall and a number of overall violations of the design rules. An interactive rule database is formed having statistics associated with the rule usage rate for subsequent implementation in an integrated circuit.