Pre-silicon Design Rule Evaluation via 3D TCAD Simulation
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Solution Overview
Problem
Developing optimal design rule sets for new or significantly changed semiconductor fabrication processes is challenging due to the difficulty in predicting the impact of changing design rules on circuit performance, often resulting in unnecessarily strict rules that leave potential performance and area gains unexploited, especially in the early stages of technology development where reliable test structures cannot be fabricated.
Innovation Solution
A black-box behavioral model approach combined with predictive 3D TCAD characterization of library cells is used to simulate the performance of ring oscillators, allowing for the evaluation of multiple design rule sets before actual silicon transistors are fabricated, using high precision models like NEGF or Subband Boltzmann to develop drift-diffusion models of transistors and characterize ring oscillator stages, which can be quickly evaluated and parallelized to test hundreds of design rule sets simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design rules are made strict to ensure yield, then manufacturing reliability is improved, but device performance and area efficiency deteriorate
Solution Approach 1:
The patent performs preliminary simulation and evaluation of design rule sets using predictive 3D TCAD characterization before actual silicon fabrication. By simulating the fabrication process and evaluating circuit performance in advance, the method identifies optimal design rules that balance yield and performance without requiring multiple iterative silicon trials.
Solution Approach 2:
The patent creates virtual copies of the fabrication process through predictive 3D TCAD simulation. Instead of physically fabricating multiple test structures to evaluate different design rules, the method uses computational models to replicate the fabrication process and predict outcomes, allowing rapid evaluation of numerous design rule sets without consuming physical materials or equipment time.
2Measurement precision
If multiple test structures are manufactured to evaluate design rules, then measurement precision is improved, but loss of time and productivity deteriorate
Solution Approach 1:
The patent replaces physical test structure fabrication with virtual simulations. Predictive 3D TCAD models replicate the behavior of actual fabricated structures, allowing accurate evaluation of design rules without the time-consuming iterative process of manufacturing, measuring, and analyzing physical test chips.
Solution Approach 2:
The patent performs design rule evaluation in advance through simulation before committing to actual fabrication. By predicting circuit performance and identifying optimal design rules upfront, the method eliminates the need for time-consuming sequential trials of multiple design rule sets on physical silicon.
3Area of moving object
If design rules are optimized for performance, then device area efficiency is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent uses predictive simulation to evaluate how fabrication variability affects performance under different design rules before fabrication. This allows identification of design rules that achieve area optimization while maintaining sufficient margin against manufacturing variability, balancing performance and robustness in advance.
Solution Approach 2:
The patent systematically varies design rule parameters (such as spacing, width, and alignment tolerances) in simulations to identify optimal values. By changing these parameters in the virtual model and evaluating their impact on both area and performance under variability, the method finds the sweet spot where area efficiency and manufacturing robustness are both satisfied.
Data Source
AI summary
Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.