Design Verification Merging Identical Coverpoints
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Solution Overview
Problem
Achieving full coverage in design verification of processing devices through logic simulation is a time-consuming and difficult process, especially when dealing with large designs containing numerous replicated circuits, as it requires generating and applying a large amount of stimulus to ensure all coverpoints are hit.
Innovation Solution
A method that merges coverage results for sets of identical function blocks, where if one coverpoint is covered in the simulation, all equivalent coverpoints in the set are considered covered, reducing the time required for verification by eliminating the need for independent coverage of each coverpoint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic simulation is performed to achieve full coverage of all coverpoints in designs with replicated circuits, then verification completeness is improved, but verification time increases significantly
Solution Approach 1:
The patent merges coverage results from multiple identical function blocks by consolidating their coverpoints into groups. When any function block in a set covers a coverpoint, the merged result marks that coverpoint as covered for the entire group, eliminating redundant verification efforts while maintaining complete coverage assurance.
2Measurement precision
If stimulus is generated to cover all coverpoints independently in replicated circuits, then coverage accuracy is improved, but stimulus quantity and complexity increase
Solution Approach 1:
The patent creates a universal coverage tracking mechanism that handles multiple identical function blocks simultaneously. The merged coverage result system serves all replicated circuits with a single unified approach, where stimulus applied to one instance contributes to the coverage of equivalent coverpoints across all instances, reducing overall stimulus complexity while maintaining accurate coverage measurement.
Data Source
AI summary
A method and system for improved design verification for a data processing device when performing a logic simulation. The system identifies certain corresponding coverpoints at different points in results of a logic simulation for a design. Using coverage results obtained for the design, a merging of the results is performed for the certain corresponding coverpoints in the design. In the merged results, a coverpoint is considered as covered if at least one corresponding coverpoint is covered during the logic simulation.