Deskew Circuit Reduces Power in Multi-Lane Signal Receiver
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Solution Overview
Problem
Conventional multi-lane receivers consume significant power due to the need for multiple clock and data recovery (CDR) circuits to address phase skew in high-speed data transmission systems.
Innovation Solution
A signal receiving apparatus with a CDR circuit and deskew circuits, where the deskew circuits adjust phase skew using a single clock signal from one lane to generate output signals for other lanes, eliminating the need for multiple CDR circuits and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CDR circuits are disposed in each lane to extract clock signals and eliminate phase skew, then the phase skew problem is solved, but the power consumption becomes significant
Solution Approach 1:
The patent merges the clock signal extraction function from multiple lanes into a single CDR circuit that operates on one lane, while other lanes use deskew circuits that utilize the extracted clock signal. This consolidation reduces the total number of CDR circuits from N (one per lane) to just one, significantly lowering power consumption while maintaining phase skew elimination across all lanes.
Solution Approach 2:
The single CDR circuit performs the clock signal extraction function for all lanes universally, and the deskew circuits across different lanes share this common clock signal. This multi-functional approach allows one CDR circuit to serve multiple purposes that would otherwise require separate circuits in each lane, reducing overall power consumption.
2Reliability
If multiple CDR circuits are disposed in each lane to extract timing information, then timing recovery is achieved, but the device complexity increases
Solution Approach 1:
The patent combines multiple CDR circuits into a single CDR circuit that extracts timing information from one lane, while other lanes use deskew circuits that reference the extracted clock signal. This merging reduces the number of CDR circuits from N to 1, significantly reducing device complexity while maintaining timing recovery capability.
Solution Approach 2:
The single CDR circuit acts as an intermediary that extracts the clock signal from one lane, and this extracted signal serves as a common reference for deskew circuits in other lanes. This intermediary approach eliminates the need for multiple CDR circuits while maintaining timing information extraction across all lanes.
Data Source
AI summary
A signal receiving apparatus includes a clock and data recovery (CDR) circuit, a first sampler, and at least one deskew circuit. The CDR circuit receives a first signal through a first lane of the signal receiving apparatus and decodes the first signal to extract a first clock signal from the first signal. The CDR circuit provides the first clock signal to the first sampler and the least one deskew circuit. The first sampler receives the first signal through the first lane of the signal receiving apparatus. The first sampler samples the first signal based on the first clock signal to generate a first output signal. The at least one deskew circuit receives a second signal through at least one second lane of the signal receiving apparatus and adjusts a phase skew between the first clock signal and the second signal so as to generate a second output signal.