Deskew DLL State Machine to Prevent False Edge Locking
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Solution Overview
Problem
Modern microprocessors with multiple clock domains face issues in deterministic data transfer due to supply-noise induced jitter, which can cause the state machine to falsely align the clock with the incorrect edge of the reference clock, leading to irrecoverable states and incorrect locking.
Innovation Solution
The implementation of two additional phase detectors that sample the clock signal at specific delays relative to the rising and falling edges of the reference clock, allowing the state machine to determine proximity to the falling edge and adjust the clock delay to ensure locking only to the rising edge, thereby preventing false locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single phase detector is used to align the clock to the reference clock edge, then the device complexity is reduced, but the reliability of clock locking deteriorates due to false locking on incorrect edges under jitter conditions
Solution Approach 1:
The single phase detection function is segmented into three separate phase detectors, each responsible for detecting different edge combinations (rising-rising, rising-falling, falling-rising). This segmentation allows the system to distinguish between true lock and false lock conditions by analyzing multiple detection results, thereby improving reliability without significantly increasing overall system complexity.
Solution Approach 2:
A state machine is introduced as an intermediary component that processes the outputs from the three phase detectors and determines the correct locking state. The state machine analyzes the detection results and controls the delay line adjustments, acting as a mediator that resolves the ambiguity between true and false locking conditions under jitter, thereby improving reliability while managing complexity.
2Manufacturing precision
If the delay line increment is made smaller to improve alignment precision, then the manufacturing precision of clock alignment is improved, but the productivity of lock acquisition deteriorates due to more incremental steps required
Solution Approach 1:
The delay line increment is made dynamic rather than fixed. The system uses a coarse increment mode for initial lock acquisition to achieve fast convergence, and then switches to a fine increment mode for precise alignment. This dynamic adjustment of increment size allows the system to achieve both fast acquisition speed and high alignment precision, resolving the contradiction between productivity and manufacturing precision.
Data Source
AI summary
A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.