Deskew FIFO Buffer Initialization via Slow Mode
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Solution Overview
Problem
Existing deskew FIFO designs face challenges in accommodating substantial clock skew drifts and require complex initialization procedures, including custom dynamic logic and continuously adjustable delay lines, limiting their applicability and robustness in modern ASIC and CPU designs.
Innovation Solution
A source-synchronization interface circuit with a sender synchronous-to-asynchronous protocol converter and an asynchronous FIFO buffer, utilizing regenerative gain to resolve metastability, and control logic that initializes the FIFO in a slow mode to ensure phase synchronization, avoiding dropped edges and tolerating skew drifts, implemented using standard components for simplicity and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-stage handshaking FIFO with custom dynamic logic is used, then metastability is resolved after initialization, but the circuit complexity increases and adaptability to design flows is reduced
Solution Approach 1:
The patent uses standard static logic components instead of custom dynamic logic, sacrificing some metastability resolution capability in exchange for using simpler, more readily available components that work reliably in standard design flows
Solution Approach 2:
The FIFO interface is designed to work with standard logic components that can be used across multiple design contexts and clock domain configurations, rather than requiring specialized custom logic circuits
2Measurement precision
If continuously adjustable delay lines are used for initialization, then phase synchronization is achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent performs phase synchronization during an initialization phase before normal operation begins, using fixed delay elements rather than continuously adjustable ones. This preliminary action establishes the correct phase relationship without requiring complex adjustable infrastructure
Solution Approach 2:
The delay characteristics are dynamically selected during initialization based on detected phase relationships, but the physical delay elements themselves remain fixed. This provides the flexibility needed for synchronization without the manufacturing complexity of continuously adjustable delay lines
3Device complexity
If a single FIFO stage is used, then the architecture is simple, but the ability to tolerate substantial skew drifts is limited
Solution Approach 1:
The patent divides the FIFO interface into multiple stages, each handling a portion of the data path. This segmentation allows each stage to tolerate certain amounts of skew drift independently, providing cumulative tolerance across the entire interface while maintaining manageable complexity in each individual stage
4Ease of manufacture
If standard components are used instead of custom logic, then ease of manufacture and adaptability improve, but metastability resolution capability may be reduced
Solution Approach 1:
The patent incorporates feedback mechanisms using standard logic components to detect and correct phase misalignment and metastability conditions. The feedback loops use conventional flip-flops and logic gates to sense unstable states and trigger corrective actions, achieving reliable metastability resolution without custom dynamic logic
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances system performance by eliminating the need for custom logic and adjustable delay lines, improving skew tolerance and reducing costs, while ensuring reliable operation across a wide range of clock periods and phases.
Implementation Method 1
the sender synchronous-to-asynchronous protocol converter has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock
Data Source
AI summary
A source-synchronization interface circuit includes: a sender synchronous-to-asynchronous protocol converter that receives sender data and a sender clock and that has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous FIFO buffer with multiple stages that conveys phase information and data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; and a receiver synchronous-to-asynchronous protocol converter that receives the receiver clock and that has regenerative gain to resolve metastability during the phase synchronization. Moreover, the source-synchronization interface circuit includes control logic that initializes the source-synchronization interface circuit by operating the stages in the asynchronous FIFO buffer in a slow mode having a cycle time less than a data-transfer period for a predetermined number of clock cycles, and subsequently operating the stages in a normal mode having a cycle time that is less than that for the slow mode.