De-skew Circuit for PCIe Multi-lane Timing Alignment
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Solution Overview
Problem
In PCIe multi-lane data transmission systems, lane-to-lane skew causes unaligned timing of input data streams, leading to incorrect parsing of transaction and data link layer packets by the media access control, necessitating a solution to synchronize data across multiple lanes.
Innovation Solution
A de-skew circuit comprising N data synchronization circuits and a controller, where each data synchronization circuit includes a command detector and a buffer, synchronizes input data streams by storing them based on single lane conditions and outputting them as timing-aligned streams when a global lane condition is met, ensuring aligned timing across all lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-lane data transmission is implemented to increase bandwidth, then data transmission capacity is improved, but lane-to-lane skew causes timing misalignment between lanes
Solution Approach 1:
The patent applies preliminary action by detecting timing skew between lanes using training sequences before normal data transmission begins. The de-skew circuit pre-adjusts the timing of each lane based on detected skew amounts, establishing proper synchronization before actual data transfer. This ensures timing alignment is achieved in advance, preventing misalignment issues during productive transmission.
Solution Approach 2:
The patent introduces a de-skew circuit as an intermediary component between the PCIe physical layer and the media access control layer. This intermediary circuit receives skewed data from multiple lanes, applies timing adjustments based on detected skew, and outputs synchronized data streams. The de-skew circuit acts as a mediator that resolves the timing misalignment problem without affecting the overall multi-lane transmission architecture.
2Productivity
If data streams from multiple lanes are processed simultaneously, then processing efficiency is improved, but unaligned timing causes incorrect packet parsing
Solution Approach 1:
The patent implements feedback by using training sequences transmitted during link initialization to measure timing skew between lanes. The de-skew circuit detects the skew amount and uses this feedback information to adjust timing offsets for each lane. This closed-loop feedback mechanism ensures that timing adjustments are based on actual measured conditions, achieving reliable synchronization before normal data processing begins.
Solution Approach 2:
The patent applies preliminary action by performing timing skew detection and adjustment during the training phase before normal data transmission. The de-skew circuit pre-synchronizes all lanes using training sequences, establishing proper timing alignment in advance. This preliminary synchronization ensures that when actual data packets are processed simultaneously, they are properly aligned and can be parsed correctly without timing-related errors.
3Device complexity
If timing skew between lanes is not corrected, then device complexity is reduced, but receiver operations fail due to unaligned data streams
Solution Approach 1:
The patent applies segmentation by dividing the de-skew function into separate processing stages: training sequence detection, skew measurement, timing adjustment calculation, and actual data synchronization. The de-skew circuit processes each lane independently, detecting skew for individual lanes and applying specific adjustments to each. This segmented approach breaks down the complex synchronization problem into manageable per-lane operations, reducing overall system complexity while maintaining reliability.
Data Source
AI summary
A de-skew circuit, a de-skew method and a receiver are provided. The de-skew circuit includes N data synchronization circuits and a controller. An nth data synchronization circuit among the N data synchronization circuits includes an nth command detector and an nth buffer. The nth command detector changes an nth command detection signal when an nth input data stream satisfies a single channel condition. The nth buffer stores the nth input data stream in response to a voltage change of the nth command detection signal. The controller receives the nth command detection signal and changes a pop signal when a global channel condition is satisfied. The nth buffer outputs an nth timing-aligned data stream in response to a voltage change of the pop signal.