Deskewed Multi-Die Package With Matched Propagation Delay
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Solution Overview
Problem
Multi-chip microelectronic packages face challenges in minimizing signal propagation delays and skew, which affect the performance and frequency of signal transmission between chips, leading to increased power consumption and reduced bandwidth.
Innovation Solution
The design of microelectronic packages with strategically placed terminals and conductive structures ensures that signals experience matched propagation delays across all connections, reducing skew by structuring traces and conductive elements to maintain consistent signal timing across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional chip packaging is used, then the chip occupies a large area on the circuit panel, but the connection length and signal propagation delay increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, where multiple chips are vertically arranged and connected through the substrate thickness direction. This dimensional change allows chips to be closely positioned in the vertical axis while maintaining short horizontal connection paths, thereby reducing signal propagation delay despite occupying minimal panel area.
Solution Approach 2:
The patent implements a nested structure where multiple chips are stacked within a compact package volume, with each chip positioned at different vertical levels. The connection substrate acts as a common platform that integrates multiple chip layers, allowing dense packing while maintaining short inter-chip connection lengths through vertical vias and through-substrate conductors.
2Area of stationary object
If multiple chips are packed into a small space, then compactness is improved, but signal skew and propagation delay differences increase
Solution Approach 1:
The patent employs delay matching techniques where connection paths are designed to have equal electrical lengths from a common reference point on the substrate to corresponding contacts on different chips. This equipotential approach ensures that signals arrive at synchronized times despite the compact multi-chip arrangement, thereby maintaining signal timing consistency.
Solution Approach 2:
The patent applies different connection path designs for different signal groups, with each path optimized for its specific routing requirements. By locally adjusting trace lengths, via configurations, and conductor geometries, the patent achieves matched propagation delays across all chips while maintaining overall package compactness.
3Adaptability or versatility
If connection paths are made longer to reach multiple chips, then more chips can be connected, but power consumption and impedance increase
Solution Approach 1:
The patent utilizes the vertical dimension to connect multiple chips through short via paths and through-substrate conductors, avoiding long lateral routing. This three-dimensional connection approach enables multiple chips to be interconnected with minimal connection length, thereby reducing power consumption and impedance while maintaining high adaptability.
Solution Approach 2:
The patent introduces a connection substrate as an intermediary platform that provides common connection points and short vertical pathways to multiple chips. This mediator structure enables efficient signal distribution to numerous chips without requiring long direct connections from each chip, thereby reducing overall power consumption and impedance.
Data Source
AI summary
A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.