Destroyable Test Circuit for Integrated Circuit Security

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Solution Overview

Problem

Integrated circuit chips, particularly those with testing ports like the TAP interface, are vulnerable to hacker access, allowing extraction of security keys and private information, compromising information security systems.

Innovation Solution

A method involving the formation of a destroyable circuit on the chip, which is tested and then destroyed, eliminating the testing port as a source of vulnerability by removing or disabling the test circuitry, such as the TAP controller, using techniques like laser ablation or e-fuse blowing, ensuring the integrity of the device circuitry remains intact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a testing port (TAP interface) is incorporated in the integrated circuit for manufacturing testing, then the chip can be screened for process defects and functional confirmation, but the testing port becomes a vulnerability that hackers can exploit to extract security keys and private information

Engineering Contradiction:
Improvemanufacturing testing capabilityVSAvoidsecurity vulnerability
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by destroying the test circuitry immediately after manufacturing testing is completed. The destroyable circuit is eliminated before the chip is shipped to customers, so the security vulnerability never exists in the final product while still allowing manufacturing testing to occur. This resolves the contradiction by performing the necessary testing action in advance and then removing the harmful element.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the test circuitry from the final product by designing it as separable destroyable circuit. The test controller and associated test logic are implemented in a manner that allows them to be physically removed or disabled after serving their manufacturing purpose. This extraction eliminates the security vulnerability while preserving the manufacturing testing capability.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If the testing port is left intact in the finished chip, then no additional destruction steps are needed in the manufacturing process, but the chip remains vulnerable to information extraction attacks

Engineering Contradiction:
Improvemanufacturing process efficiencyVSAvoidinformation security
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The destruction of test circuitry is performed as a preliminary action immediately after testing and before shipping. This additional step, while adding some process time, ensures that security vulnerabilities are eliminated. The productivity loss is minimal compared to the security benefits, and the destruction process is automated and integrated into the existing manufacturing flow.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the potentially harmful test circuitry into a beneficial security feature by destroying it. The same circuitry that could be exploited by hackers is transformed into a security mechanism through controlled destruction. This approach turns what would be a continuous vulnerability into a temporary manufacturing aid that is then eliminated.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If destroyable circuitry is added to the chip for post-testing destruction, then security is enhanced by eliminating the testing port vulnerability, but the device complexity increases

Engineering Contradiction:
Improveinformation securityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the destroyable test circuitry with the existing device circuitry areas. The test controller is integrated alongside the device logic, and the destruction mechanism is combined with existing chip structures. This merging approach minimizes the increase in device complexity while still providing the security benefit of eliminable test ports.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The destroyable circuit serves multiple functions: it enables manufacturing testing, provides a target for security-oriented destruction, and can be integrated with existing device logic. By making the test circuitry multi-functional and versatile in its design, the patent reduces the need for separate dedicated destruction circuits, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents unauthorized access by eliminating the testing port's potential for exploitation, enhancing the security of integrated circuit chips by ensuring that sensitive information cannot be obtained post-manufacturing, thereby fortifying information security systems.

Implementation Method 1

destroying the destroyable circuit subsequent to testing the at least one operational aspect of the device circuitry... using techniques like laser ablation

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS9343377B1Test then destroy technique for security-focused semiconductor integrated circuits
Publication Date: 2016.05.17 GOOGLE LLC
  • US9343377B1 patent drawing
  • US9343377B1 patent drawing
  • US9343377B1 patent drawing

AI summary

A method includes forming an integrated circuit device having device circuitry disposed in a device circuitry area on a substrate and a destroyable circuit formed in a destroyable circuitry area on the substrate; testing at least one operational aspect of the device circuitry using the destroyable circuit; and destroying the destroyable circuit subsequent to testing the at least one operational aspect of the device circuitry.