Destructive Read Memory Circuit Bandwidth Optimization
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Solution Overview
Problem
Memory circuits with destructive read types, such as MRAM and FeRAM, lose stored data when reading, necessitating a write-back process to retain data, which can overutilize bandwidth and power due to the back-and-forth data flow between memory and processing circuits.
Innovation Solution
Implementing a memory circuit with a control mechanism that distinguishes between data requiring write-back and not, using a read-write-back command to directly write data back to memory cells while transmitting it to the processing circuit, reducing the need for redundant data transmission and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If data is read from memory cells in a destructive read type memory circuit, then data can be accessed and transmitted to the processing circuit, but the stored data is lost and requires a write-back process
Solution Approach 1:
The patent combines the read operation and write-back operation into a single integrated process. When data is read from memory cells, the same data path and control mechanisms are used to automatically rewrite the data back to the original memory location, eliminating the need for separate read and write-back operations. This merging reduces bandwidth utilization and power consumption while ensuring data is preserved.
Solution Approach 2:
The patent performs the write-back action in the same operational cycle as the read operation. By preparing the write-back path and control signals simultaneously with the read operation, the system eliminates redundant data transmission. The data is read, held temporarily, and written back to the same memory cell within the same operational sequence, preventing data loss without requiring additional bandwidth.
2Ease of operation
If data is read from memory cells and transmitted to the processing circuit, then data can be processed, but power consumption increases due to the back-and-forth data flow
Solution Approach 1:
The patent merges the read and write-back operations into a single integrated process that occurs within the same operational cycle. By combining these operations, the system eliminates redundant data transmission paths and reduces the number of active signal lines, thereby lowering power consumption while maintaining full data processing capability.
Solution Approach 2:
The patent maintains continuous data flow within the memory circuit by performing read and write-back operations in an uninterrupted sequence. Data is read from memory cells, held in temporary storage, and immediately written back to the same location without interruption. This continuous operation reduces the need for repeated activation of power-intensive components and minimizes overall power consumption.
3Reliability
If a write-back process is implemented to retain data after reading, then data can be preserved in memory cells, but bandwidth is overutilized due to redundant data transmission
Solution Approach 1:
The patent combines the read operation and write-back operation into a single integrated process. The same data path and control mechanisms are used for both operations, and they occur within the same operational cycle. This merging ensures data is preserved in memory cells while eliminating redundant data transmission, as the data flows through the system only once rather than being transmitted separately for reading and writing.
Data Source
AI summary
According to one embodiment, a memory circuit includes a plurality of nonvolatile memory cells and a control circuit. Each of the plurality of nonvolatile memory cells loses stored data when the stored data is read. The control circuit reads data from a first memory cell among the plurality of memory cells as designated by a first instruction but does not write the data read from the first memory cell back to the first memory cell after the first instruction is received. The control circuit reads data from a second memory cell among the plurality of memory cells as designated by a second instruction and writes the data read from the second memory cell back to the second memory cell after the second instruction is received.