Detecting Memory Defects via Current Leaks During Erase Operations
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Solution Overview
Problem
Existing memory sub-systems face challenges in detecting defects during erase operations, particularly in multi-plane devices, where defects may not be detectable until they lead to failures in program or read operations, affecting memory device reliability and endurance.
Innovation Solution
Implementing defect detection mechanisms that leverage the voltages used during erase operations to identify current leaks and voltage drops between components, allowing for the identification of defects during sub-operations such as erase pulse and verify operations, thereby improving defect detection and memory device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If defect detection is performed during erase operations in multi-plane memory devices, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines defect detection functionality with existing erase operations in multi-plane memory devices. By integrating detection mechanisms into the erase pulse and verify operations that already exist, the system achieves defect detection without adding completely separate detection pathways, thus improving reliability while limiting the increase in device complexity.
Solution Approach 2:
The erase operations in multi-plane memory devices are made multi-functional by enabling them to perform both their traditional data erasure function and an additional defect detection function. This allows the same hardware infrastructure to serve dual purposes, improving reliability while avoiding the need for dedicated defect detection circuits that would increase complexity.
2Manufacturing precision
If defect detection is performed during erase operations, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent merges defect detection measurements with the existing erase operation timeline. By utilizing the same time window and operational phases (erase pulse and verify) for both erasure and detection purposes, the system achieves precise defect identification without requiring separate detection time slots that would extend the overall operation duration.
Solution Approach 2:
The defect detection process maintains continuity with the erase operation by performing measurements during the active erase phases rather than interrupting or pausing the operation. This allows the useful action of erasing to continue uninterrupted while defect detection measurements are taken concurrently, improving detection precision without significant time penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances defect detection capabilities during erase operations, improving memory device reliability and endurance by identifying defects before they cause failures, leading to improved performance and extended lifespan of memory devices.
Implementation Method 1
leverage the voltages used during erase operations to identify current leaks and voltage drops between components
Data Source
AI summary
A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including initiating an erase operation performed with respect to the memory array, identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array, and causing an indication of the at least one defect to be generated. The erase operation includes a select gate scan sub-operation.