Detecting Slow-Erasing Memory Blocks via Upper Tail Voltage Analysis
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Solution Overview
Problem
Existing memory devices face challenges in detecting slow-erasing blocks during erase operations, which can lead to uncorrectable read errors and degrade over time, as current methods are either invasive, time-consuming, or unable to identify slow-erasing blocks in situ.
Innovation Solution
The implementation of an additional verify test in specified erase-verify iterations to detect slow-erasing blocks by checking the position of the upper tail of the threshold voltage distribution of memory cells, allowing for in situ detection and reducing time penalties through optimized verify test sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional erase operations are used without additional verify tests, then the erase process is simple and fast, but slow-erasing blocks cannot be detected leading to uncorrectable read errors
Solution Approach 1:
The patent applies preliminary action by performing an additional verify test at a specified erase-verify iteration before the erase operation is complete. This early verification checks the upper tail of the threshold voltage distribution to identify slow-erasing blocks, allowing detection before finalizing the erase operation. The specify iteration is determined based on expected erase characteristics, enabling early detection without completing all standard verify iterations.
Solution Approach 2:
The patent implements partial action by adding only one additional verify test at a specific iteration rather than increasing the frequency or number of all verify tests. This selective approach focuses verification resources on the most critical detection point (when slow-erasing blocks become distinguishable), achieving reliable detection while minimizing the time penalty compared to comprehensive verification at every iteration.
2Reliability
If multiple verify tests are performed at every iteration, then slow-erasing blocks can be detected reliably, but the erase operation becomes time-consuming
Solution Approach 1:
The patent applies partial action by performing the additional verify test only at a specified erase-verify iteration rather than at every iteration. This selective verification targets the critical moment when slow-erasing blocks become distinguishable through threshold voltage distribution analysis, achieving reliable detection while avoiding the time penalty of excessive verification at all iterations.
Solution Approach 2:
The patent uses parameter changes by monitoring the upper tail of the threshold voltage distribution at a specific erase-verify iteration. By analyzing this particular parameter (upper tail position) at a strategically chosen iteration point, the method achieves reliable detection of slow-erasing blocks without requiring multiple comprehensive verify tests, thus maintaining erase operation speed.
3Reliability
If invasive testing methods are used to detect slow-erasing blocks, then detection can be performed, but the testing process is complex and disruptive to normal operations
Solution Approach 1:
The patent applies self-service by utilizing the memory device's own existing verify test circuitry and threshold voltage distribution analysis capabilities to detect slow-erasing blocks. The method leverages the device's inherent operational characteristics and built-in verification mechanisms, eliminating the need for external invasive testing equipment or complex test procedures. The detection is performed using the device's normal operational parameters and circuits.
Solution Approach 2:
The patent implements universality by designing the detection method to work within the existing erase-verify operational framework of the memory device. The same verify test circuits and threshold voltage analysis mechanisms used for normal erase verification are repurposed for slow-erasing block detection, allowing a single system to serve multiple functions (normal verification and defect detection) without adding complex specialized testing infrastructure.
Data Source
AI summary
Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.