Detecting Selectivity Loss Defects in Epitaxial Stressor Regions
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Solution Overview
Problem
The existing methods for applying stress to channel regions of MOS devices to improve carrier mobility often result in selectivity loss defects due to reactions between epitaxial growth precursors and gate spacers, which are difficult to detect and remove, leading to performance issues and manufacturing inefficiencies.
Innovation Solution
A method involving the use of a reference wafer with epitaxially formed semiconductor material in patterned openings, subjected to wavelength-dispersive X-ray spectroscopy (WDS) and current-voltage (IV) measurements to detect and locate selectivity loss defects, allowing for precise and rapid identification without damaging the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth process is used to form stressor regions, then carrier mobility is improved through stress application, but selectivity loss defects occur due to precursor reactions with gate spacers
Solution Approach 1:
The patent applies preliminary action by performing a cleaning process on the gate spacers before the epitaxial growth of stressor regions. This preventive cleaning removes potential reaction sites on the gate spacers that would otherwise cause selectivity loss defects during the subsequent epitaxial growth process, thereby maintaining both carrier mobility improvement and defect-free fabrication
2Manufacturing precision
If typical cleaning processes are used to remove selectivity loss defects, then some defects may be removed, but the defects are difficult to remove completely and quickly
Solution Approach 1:
The patent performs cleaning of gate spacers as a preliminary step before epitaxial growth, preventing selectivity loss defects from forming in the first place. This proactive approach eliminates the need for time-consuming post-growth defect removal processes, achieving both high manufacturing precision and efficient production timing
3Productivity
If rapid detection of selectivity loss defects is needed, then manufacturing efficiency improves, but existing detection methods are insufficiently quick and precise
Solution Approach 1:
The patent replaces mechanical or slow optical inspection methods with electrical measurement techniques to detect selectivity loss defects. By measuring electrical properties such as current-voltage characteristics, the system achieves both rapid detection speed and high precision in identifying defects, thereby improving overall productivity without sacrificing measurement accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables early detection and localization of defects, reducing manufacturing cycle times, minimizing waste, and maintaining substrate integrity, thereby enhancing the efficiency and reliability of the semiconductor device production process.
Implementation Method 1
epitaxially forming a semiconductor material within the plurality of openings
Implementation Method 2
epitaxially growing stressor regions in the recesses using an epitaxial growth process
Implementation Method 3
subjected to wavelength-dispersive X-ray spectroscopy (WDS) and current-voltage (IV) measurements
Implementation Method 4
wavelength-dispersive X-ray spectroscopy (WDS)
Implementation Method 5
An annealing may also be performed
Implementation Method 6
it expands after annealing and applies a compressive stress to the channel region
Implementation Method 7
it contracts after annealing and applies a tensile stress to the channel region
Data Source
AI summary
A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison.