Flat Panel Detector Storage Capacitor Vertical Stacking

The patent introduces a third-dimensional stacking architecture where capacitor electrodes are arranged in multiple layers (first capacitor electrode layer, second capacitor electrode layer, third capacitor electrode layer) vertically above each other. This vertical stacking enables increased storage capacitor capacity without expanding the planar pixel area, thereby maintaining the aperture ratio while reducing parasitic capacitance impact on signal quality.

The patent implements nested capacitor structures where multiple capacitor electrode layers are positioned within the same pixel region. The first, second, and third capacitor electrode layers are nested vertically, with each layer contributing to the total capacitance. This nesting approach allows the storage capacitor to achieve higher capacity within the confined pixel area without degrading the aperture ratio or significantly increasing parasitic capacitance.

The patent transitions from a planar two-dimensional capacitor layout to a three-dimensional vertical stacking configuration. Multiple capacitor electrode layers are arranged vertically within the same footprint area, enabling the storage capacitor capacity to increase while the aperture ratio (the ratio of photoelectric conversion layer area to total pixel area) remains preserved.

The storage capacitor is segmented into multiple discrete capacitor electrode layers (first, second, and third layers) that can be independently formed and positioned. This segmentation allows the total capacitance to be distributed across multiple layers, achieving the required storage capacity without requiring a single large-capacitor structure that would consume excessive pixel area and reduce the aperture ratio.