Deterministic BIST Using Compressed Test Patterns and Bit Inversion
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Solution Overview
Problem
Current deterministic built-in self-test (BIST) schemes face challenges in achieving flexible trade-offs between test coverage and test data volume while maintaining reasonable test time, especially in ultra-large-scale designs, where the size of on-chip test data memory affects test time and coverage.
Innovation Solution
A deterministic BIST system is developed that generates clusters of test patterns by inverting bits of a parent test pattern corresponding to scan shift clock cycles, using a decompressor and controller to output compressed test patterns, allowing for efficient decompression and fault detection with reduced on-chip memory and test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deterministic test patterns are stored on chip in compressed form, then test data volume is reduced, but test time increases due to decompression and pattern generation overhead
Solution Approach 1:
The patent pre-computes and stores compressed deterministic test patterns and their decompression control signals in on-chip memory before actual testing. This preliminary preparation allows the test patterns to be quickly decompressed and applied during testing, reducing the overall test time despite the initial storage requirement.
Solution Approach 2:
The patent uses a decompressor that generates multiple test patterns by copying and modifying a single compressed seed pattern. The decompressor creates derivative patterns by inverting bits at different scan shift clock cycles, effectively multiplying the test coverage from a single stored pattern without requiring proportional increases in storage.
2Quantity of substance
If weighted random patterns are used to reduce storage volume, then test data volume is reduced, but fault coverage decreases for random-pattern-resistant faults
Solution Approach 1:
Instead of using random patterns and hoping to cover faults, the patent inverts the approach by systematically generating deterministic patterns that are guaranteed to cover specific fault types. The decompressor inverts bits of the compressed pattern at controlled intervals to create derivative patterns, ensuring comprehensive coverage of random-pattern-resistant faults while maintaining compact storage.
Solution Approach 2:
The patent changes the parameter of pattern generation from random to deterministic by using a controlled inversion process. The decompressor modifies the compressed pattern by inverting bits at specific scan shift clock cycles, creating a systematic sequence of deterministic patterns that provide guaranteed fault coverage without the need for large volumes of random patterns.
3Reliability
If more test patterns are applied to increase fault coverage, then fault coverage is improved, but test data volume and storage requirements increase
Solution Approach 1:
The patent segments the test pattern generation into a compressed seed pattern and a set of control signals that define how to generate derivative patterns. The decompressor uses these control signals to systematically create multiple test patterns from the single compressed pattern, segmenting the storage requirement from the functional output.
Solution Approach 2:
The patent embeds multiple test patterns within a single compressed pattern structure. The decompressor extracts the compressed pattern and nested control information, then generates multiple derivative patterns by inverting bits at different scan shift clock cycles. This nesting allows multiple functional patterns to be stored in a compact form.
Data Source
AI summary
Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.