Deterministic Clock Domain Synchronization via Phase-Shifted Delay
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Solution Overview
Problem
Conventional synchronization units between different clock domains exhibit non-deterministic behavior due to varying metastable value resolutions, making it difficult to consistently debug functional failures as the same test stimulus may produce inconsistent results.
Innovation Solution
A system and method for deterministic synchronization that characterizes the relative phase difference between clock domains and configures delay elements to generate phase-shifted clocks, ensuring consistent signal transmission by avoiding metastable value sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronization units are used to transmit signals between clock domains, then signal transmission is achieved, but non-deterministic behavior occurs due to varying metastable value resolutions
Solution Approach 1:
The patent applies preliminary action by measuring the phase difference between clock domains in advance and configuring delay elements before signal transmission. This pre-characterization of phase relationships allows the synchronization unit to deterministically resolve metastable values by knowing the exact timing relationships ahead of time, eliminating non-deterministic behavior during actual signal transmission
Solution Approach 2:
The patent changes the timing parameters of clock signals by introducing configurable delay elements that adjust clock phase relationships. By modifying the phase difference parameter between clocks based on pre-measured characteristics, the system transforms metastable sampling into a deterministic process where flip-flops consistently sample at known good timing points
2Ease of operation
If same test stimulus is applied multiple times in the first clock domain, then functional debug is attempted, but inconsistent results are produced in the second clock domain due to non-deterministic behavior
Solution Approach 1:
The patent implements feedback by using pre-measured phase difference information to configure delay elements. The system feeds back the characterized timing relationships into the synchronization unit's delay configuration, creating a closed-loop system that ensures deterministic behavior. This feedback mechanism guarantees that the same test stimulus will produce consistent results across multiple applications
3Reliability
If delay elements are configured based on phase difference to achieve deterministic mode, then consistent signal transmission is obtained, but additional characterization and configuration steps are required
Solution Approach 1:
The patent performs preliminary characterization of phase differences and configures delay elements before normal operation. This one-time setup process captures timing relationships and stores them for use during subsequent signal transmissions, making the deterministic behavior achievable without adding complexity to the ongoing operation
Data Source
AI summary
One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.