Deterministic Clustering for Random Logic Utilization
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Solution Overview
Problem
Programmable integrated circuits, such as FPGAs, face inefficiencies in utilizing random logic resources, with typical utilization maxing out at 85%, leading to non-deterministic performance and wasted chip area, as existing methods to increase utilization are not applicable to random logic.
Innovation Solution
A method for achieving deterministic clustering and packing of random logic circuitry, which involves locking down cell names, obtaining location solution files, reassembling designs with best solutions, and locking these solutions to the LAB level, allowing for increased random logic utilization beyond 85% and boosting device performance by 20% or more.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packing methods are used for random logic, then device utilization reaches around 85%, but speed becomes non-deterministic and chip area is wasted
Solution Approach 1:
The patent segments the random logic design into multiple identical replicated blocks (e.g., 4 replications of a cryptographic algorithm). Each replication is independently placed and routed, allowing deterministic performance characteristics while achieving high utilization through efficient packing of these standardized segments across the device fabric.
Solution Approach 2:
The patent changes the parameter of replication count (N) to optimize both utilization and performance. By systematically varying the number of replications and their placement, the method achieves deterministic speed characteristics while maximizing device utilization beyond the conventional 85% limit.
2Productivity
If additional packing of random logic beyond 85% utilization is attempted, then device utilization increases, but device performance decreases
Solution Approach 1:
The patent merges multiple identical logic replications into a unified design that is synthesized and implemented as a single coherent system. This merging allows the design to achieve high utilization while maintaining deterministic performance, as the synthesis tool can optimize the combined structure rather than treating each replication independently.
Solution Approach 2:
The patent creates a universal replicated block structure that can be instantiated multiple times with identical characteristics. This universality allows the same design template to be efficiently packed across the device, achieving high utilization while ensuring each instance maintains deterministic performance characteristics.
3Adaptability or versatility
If random logic is packed with small design changes, then design flexibility is maintained, but speed varies significantly between compilations
Solution Approach 1:
The patent performs preliminary actions by defining the replication structure and constraints before synthesis. By pre-specifying the number of replications, their interconnections, and placement constraints, the method ensures deterministic performance while still allowing flexibility in the underlying logic design. This preliminary structuring prevents compilation-to-compilation variability.
Data Source
AI summary
Methods and apparatus for increasing the random logic utilization on a programmable device are provided. Although not completely homogeneous, the programmable device has many components that are repeated many times in an array. To help improve repeatability and packing, computer-aided design tools for compiling a circuit design for the programmable device may first lock down a synthesis cell netlist with stable naming, create location solution files (files with desired clustering granularity for stabilizing performance and reducing compile times) for selected regions of interest on the programmable device, and compose a final design with only the best solutions some of which can be imported from one location to another. Compiling a design in this way can help improve random logic utilization beyond 85% while improving circuit performance by 20% or more.