Deterministic Multi-Port Collision Detection Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional collision detection mechanisms in multi-port devices are non-deterministic, failing to accurately signal collisions and determine the specific cycle in which they occur due to the use of sequential elements like flip-flops, which violate setup and hold times, leading to uncertainty in collision timing.
Innovation Solution
The solution involves generating divided clock signals for each port, allowing for deterministic collision detection by asserting a busy signal a number of clock cycles after a collision is detected, and storing the address location in a memory register to report the collision accurately, ensuring that collisions are flagged deterministically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential elements (flip-flops) are used to capture the BUSY flag, then the collision detection mechanism can be implemented, but the setup and hold time requirements are violated leading to non-deterministic collision timing
Solution Approach 1:
The patent extracts the collision detection logic from the sequential element domain and places it in the combinational logic domain. By using a detector that operates purely on combinational logic without flip-flops, the setup and hold time violations are eliminated, allowing deterministic collision timing to be achieved while maintaining reliable collision detection.
Solution Approach 2:
The patent introduces an intermediary detector circuit that receives address and control signals from both ports and performs collision detection before the signals reach the sequential elements. This intermediary detector generates the BUSY flag deterministically, which is then captured by the sequential elements without causing timing violations.
2Loss of time
If the BUSY flag is captured in the same cycle as collision detection, then real-time collision signaling is achieved, but setup and hold time requirements are violated
Solution Approach 1:
The patent performs collision detection in advance within the same clock cycle using combinational logic, generating the BUSY flag before it needs to be captured by sequential elements. This preliminary action in the combinational logic domain allows the flag to be stable and valid for capture without violating setup and hold times, achieving both real-time signaling and reliable capture.
3Adaptability or versatility
If address comparison is performed between asynchronous port domains, then collision detection is enabled, but meta-stable conditions occur extending the time to detect collisions
Solution Approach 1:
The patent creates copies of address and control signals from both asynchronous ports and processes them in parallel through identical comparison logic. By duplicating the detection path for each port and comparing addresses in the same combinational logic stage, the patent eliminates meta-stable conditions while maintaining the ability to detect collisions between any pair of ports.
Data Source
AI summary
An embodiment of the present invention is directed to a method of deterministic collision detection involving at least two ports. The method includes receiving a read/write operation at a first data rate at a first port of a multi-port device, receiving a read/write operation at a second data rate at a second port of the multi-port device, detecting a collision between the first port and the second port if a same address space is accessed by the first port and the second port coincidentally, asserting a busy signal at least one of said first port and said second port a number of clock cycles after detecting said collision, storing an address location of said address space in a memory register, and deterministically report the collision using the address location and the number of clock cycles.