Semiconductor Hardware Nodes for Deterministic CTBV Signal Routing
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Solution Overview
Problem
Existing semiconductor device architectures struggle to efficiently transmit globally asynchronous continuous-time binary valued signals with deterministic transmission delays and support self-timed, self-controlled reconfiguration without data loss, particularly in neuromorphic computing applications like spiking neural networks.
Innovation Solution
A semiconductor device system with hard-wired connections and switching circuitries that enable deterministic propagation of CTBV signals between hardware nodes, allowing for latency-deterministic point-to-point communication paths and reconfigurable nodes for self-timed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamically routed packages with time-stamps are used to transmit CTBV signals, then routing flexibility is improved, but transmission delay increases and loses determinism
Solution Approach 1:
The system separates configuration data transmission from CTBV signal transmission by using dedicated hard-wired connections for signals and package-switched connections for configuration. This segmentation allows CTBV signals to maintain deterministic timing while configuration data provides routing flexibility.
Solution Approach 2:
The patent introduces a dedicated configuration communication path as an intermediary channel that handles routing information separately from the CTBV signal paths. This mediator enables flexible reconfiguration without interfering with the timing-critical signal transmission.
2Adaptability or versatility
If package-switched configuration communication path is used for reconfiguration, then routing flexibility is improved, but configuration data transmission speed decreases
Solution Approach 1:
The system divides communication channels into two segments: a fast dedicated path for CTBV signals and a flexible package-switched path for configuration data. Each path is optimized for its specific purpose, allowing reconfiguration without compromising signal transmission speed.
Solution Approach 2:
The configuration system operates autonomously during non-operative phases, allowing nodes to reconfigure themselves without external intervention. This self-service approach minimizes the impact on overall system performance.
3Loss of time
If hard-wired connections are used for CTBV signal transmission, then transmission delay determinism is improved, but routing flexibility deteriorates
Solution Approach 1:
The system combines static hard-wired connections for deterministic signal transmission with dynamic package-switched configuration paths. The hard-wired connections provide a stable foundation while the configurable switching circuitry adds dynamic routing capabilities when needed.
Solution Approach 2:
The patent allows the system to change its operational parameters by switching between different configuration states. The physical hard-wired connections remain fixed, but their logical routing relationships can be changed through configuration data, effectively changing system parameters without physical reconfiguration.
4Extent of automation
If self-timed reconfiguration is implemented, then system autonomy is improved, but data loss risk increases during reconfiguration phases
Solution Approach 1:
The system alternates between operative phases (signal processing) and non-operative phases (reconfiguration) in a periodic manner. During non-operative phases, nodes perform self-timed reconfiguration without processing CTBV signals, eliminating data loss risk while maintaining high system autonomy.
Solution Approach 2:
The system prepares for potential data loss by designing distinct operative and non-operative phases. Configuration changes are scheduled to occur only during non-operative phases when no signal transmission is occurring, providing a protective buffer against data loss while enabling autonomous reconfiguration.
Data Source
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AI summary
There is disclosed a semiconductor device system comprising a central controller (1) and a plurality of hardware nodes (2, 3, 4) implemented in application-specific integrated circuit, ASIC, the hardware nodes (2, 3, 4) being mutually interconnected with each other through a plurality of hard-wired connections (2.4, 3.4, 4.4) which support the transmissions of globally asynchronous continuous-time binary value, CTBV, signals, in such a way that each hard-wired connection supports the propagation of one unique CTBV signal from first transmitting hardware node connected to the hard-wired connection to at least one receiving hardware node connected to the hard-wired connection, so as to define at least one point-to-point(s) communication path between at least two hardware nodes, configured as processing nodes (2, 3), along a sequence of hard-wired connections connected to each other through at least one switching circuitry (12'). The at least one switching circuitry (12') is controlled by at least one hardware node, of the plurality of hardware nodes, which is configured as communication node, the at least one switching circuitry (12') being configured to selectably connect, based on configuration data, at least two hard-wired connections in the sequence of hard-wired connections, so as to permit the transmission of each CTBV signal along the sequence of hard-wired connections, wherein the at least one switching circuitry (12') is latency-deterministic. Each hardware node of the plurality of hardware nodes is configured to download configuration data through a package-switched configuration communication path (9).