Deterministic Data Transfer Between Asynchronous Clock Domains
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Solution Overview
Problem
Current automatic test equipment (ATE) cannot deterministically transfer data across different clock domains, particularly at high processor core speeds, leading to incomplete testing of I/O interfaces and processors, due to asynchronous clock operations and non-deterministic data transfers.
Innovation Solution
A system and method for deterministically transferring data across different clock domains by writing data to a buffer accessible by both domains and communicating a read status, allowing data to be read at the clock rate of the second domain, with additional circuits at clock domain crossings to facilitate deterministic operation in test mode, and utilizing SERDES interfaces to support high-speed I/O bandwidth while maintaining cycle accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred between clock domains with different clock rates, then the processor can operate at high core speeds, but the data transfer becomes non-deterministic and cycle accuracy is lost
Solution Approach 1:
A buffer is introduced as an intermediary component between the first clock domain and the second clock domain. The buffer receives data from the first domain at its clock rate and releases data to the second domain at its own clock rate, thereby mediating the frequency mismatch and enabling deterministic data transfer between asynchronous domains
Solution Approach 2:
The system changes the timing parameters by using enable signals controlled by status flip-flops to synchronize data transfer with the receiving clock domain's timing. This allows the buffer to operate at one clock rate while transferring data deterministically to a domain operating at a different clock rate
2Measurement precision
If ATE operates at high processor core speeds to test I/O interface performance limits, then testing accuracy improves, but the ATE cannot input or output data at such high speeds
Solution Approach 1:
The buffer acts as an intermediary that decouples the ATE's data transfer capability from the processor core's high-speed operation. The ATE can write data to the buffer at its own speed, and the buffer can read from the processor core at high speed independently, allowing the ATE to accurately test high-speed I/O interfaces without requiring the ATE itself to operate at those extreme speeds
3Ease of manufacture
If different clock domains operate asynchronously to simplify processor design, then design flexibility improves, but functional testing becomes complex and indeterministic
Solution Approach 1:
The buffer with controlled enable signals serves as a mediator that brings determinism back into asynchronous clock domains during testing. By using the enable signal controlled by the status flip-flop, the system can synchronize data transfer timing with the receiving domain's clock edges, enabling deterministic testing while maintaining the design flexibility of asynchronous operation
Solution Approach 2:
The status flip-flop is clocked periodically at the receiving clock domain's rate, creating periodic enable signals that synchronize data transfer with the receiving domain's timing. This periodic action introduces determinism into the otherwise asynchronous data transfer, enabling reliable testing
Data Source
AI summary
A system and method of deterministically transferring data from a first clock domain to a second clock domain includes writing data to a buffer, communicating a read status from the first clock domain to the second clock domain and reading data from the buffer into the second clock domain at a clock rate of the second domain. The buffer is accessible by both one or more devices in each of the first clock domain and the second clock domain and the read status is communicated from the first clock domain to the second clock domain when the second clock domain enables the read status to be communicated from the first clock domain to the second clock domain.