Deterministic Data Transfer Across Clock Domains
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Solution Overview
Problem
Current automatic test equipment (ATE) struggles to perform cycle-accurate and deterministic data transfers between processor core and I/O clock domains, especially at high speeds, due to asynchronous clock operations, leading to incomplete testing of processors and potential false flagging of defects.
Innovation Solution
A system and method for deterministically transferring data across different clock domains by synchronizing clock frequencies to a single reference clock, using read delays, training patterns, and phase-locked loops (PLLs) to align serial data lanes, ensuring cycle-accurate and deterministic data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If asynchronous clock domains are used to simplify processor design, then device complexity is reduced, but measurement precision and reliability of data transfer testing deteriorate due to indeterminism
Solution Approach 1:
The patent segments the clock domains into separate testable units with independent clock sources, allowing each domain to be tested independently while maintaining asynchronous operation. The test system is divided into a first clock domain for processor core testing and a second clock domain for I/O interface testing, enabling precise measurement without requiring synchronous operation across all domains.
Solution Approach 2:
The patent introduces an intermediary synchronization mechanism that allows deterministic data transfer between asynchronous clock domains during testing. A resynchronization counter and read delay mechanism act as intermediaries to align data transfer timing, enabling cycle-accurate testing while maintaining the asynchronous design benefits.
2Productivity
If ATE operates at high processor core speeds to test performance limits, then productivity is improved, but reliability of data transfer testing deteriorates due to inability to input/output data accurately
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where the ATE can operate at different clock rates depending on the test requirements. The system can switch between high-speed operation for performance testing and synchronized operation for accurate data transfer verification, allowing both high productivity and high reliability modes to coexist.
Solution Approach 2:
The patent changes the timing parameters of data transfer by introducing read delays and resynchronization mechanisms that adjust the effective data transfer timing. This allows the ATE to maintain accurate data input/output even when operating at high processor core speeds by dynamically modifying the timing parameters of the data transfer protocol.
3Measurement precision
If cycle-accurate deterministic testing is implemented to improve measurement precision, then reliability of defect detection is improved, but device complexity and test time increase
Solution Approach 1:
The patent extracts the synchronization and resynchronization functionality into separate dedicated circuits and control logic. The read delay mechanism and resynchronization counter are implemented as independent modules that can be isolated and tested separately from the main processor logic, reducing the overall complexity of implementing cycle-accurate testing.
Solution Approach 2:
The patent performs preliminary synchronization actions before actual data transfer testing begins. The system establishes deterministic timing relationships and synchronizes clock domains in advance through resynchronization commands, ensuring that subsequent data transfer tests can proceed with high precision without requiring complex real-time synchronization during the actual testing.
4Reliability
If functional testing with instruction set emulation is used to validate processor, then reliability of processor validation is improved, but productivity and test time worsen
Solution Approach 1:
The patent segments the validation process into two distinct phases: a functional testing phase that emulates instruction sets for comprehensive validation, and a performance testing phase that uses simplified deterministic data transfer protocols for rapid testing. This segmentation allows the system to achieve high reliability through functional testing while maintaining high productivity through optimized performance testing.
Solution Approach 2:
The patent creates simplified copies of the data transfer protocol specifically for performance testing, rather than using the full complex instruction set emulation for all testing. This simplified protocol maintains the essential deterministic timing characteristics needed for reliable validation while significantly reducing test execution time and improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables performance limit testing of individual clock domains with fewer test vectors, reducing test time and false positives by achieving cycle-accurate deterministic operation, even in high-speed environments.
Implementation Method 1
using read delays, training patterns, and phase-locked loops (PLLs) to align serial data lanes
Implementation Method 2
converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time
Data Source
AI summary
A system and method of deterministically transferring data across a first clock domain to a second clock domain includes receiving a resynchronize command, initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, counting down the plurality of read delays to zero, receiving a training pattern after the plurality of read delays count down to zero in each one of the second plurality of devices, recovering a clock data in each of the second plurality of devices, receiving a synch byte by each of the second plurality of devices, selecting one of a plurality of serial lanes as a reference lane, wherein the plurality of serial lanes couple the first clock domain to the second clock domain, initiating a write pointer, writing n bytes of serial data to a buffer and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time.