Deterministic Hardware Frame Absence Detection

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Solution Overview

Problem

Current communication standards, such as 802.1Qbv, 802.1Qci, and 802.1AS, fail to detect the absence of data frames in predetermined schedules, leading to undetected schedule drifts and errors in deterministic real-time communication systems, particularly in cyber-physical systems.

Innovation Solution

A method and hardware system that statically and periodically schedule data frames with a header containing a frame identifier and index, using flags and counters to detect frame absence and manage errors, allowing for deterministic real-time communication with low hardware costs and precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If dedicated hardware with flags and counters is implemented to detect frame absence, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improveframe absence detection precisionVSAvoidhardware structure complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The detection function is segmented into distinct hardware components: an activation flag for frame activity status, a local index counter for tracking frame occurrences, an open flag for time window status, and an error counter for missed frames. Each component handles a specific aspect of detection, improving precision while keeping individual components simple.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary hardware elements (flags and counters) that mediate between frame reception and error detection. These intermediaries store transient state information, enabling precise detection of frame absence without requiring complex continuous monitoring logic.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If error detection and correction mechanisms are added, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvecommunication reliabilityVSAvoiderror management complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback through the error counter that increments when frames are missed and triggers a fatal error flag when reaching a threshold. This feedback mechanism provides reliable error detection and correction by continuously monitoring reception status and alerting when corrections are needed, while maintaining simple counter-based logic.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs preliminary error detection by maintaining activation flags and error counters before critical failures occur. The fatal error flag is raised in advance when the error counter reaches its maximum value, allowing corrective actions to be taken before communication completely fails, thereby improving reliability without requiring complex real-time intervention.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11588611B2Deterministic hardware system for communication between at least one sender and at least one receiver, which is configured to statically and periodically schedule the data frames, and a method for managing the reception of data frames

Publication Date: 2023.02.21 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

AI summary

Method and system for managing the reception of data frames, scheduled statically and periodically, a frame includes a header provided with an identifier (id) of the frame and an index (index) representing the occurrence of the frame in a hyper-period.