Deterministic Latency Controller for High-Speed Data Links
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Solution Overview
Problem
The manual calculation of worst-case latency in high-speed interfaces like JESD204B/C is time-consuming and costly, requiring multiple system reinitializations across various process corners to ensure deterministic latency across different operating temperatures and supply voltages.
Innovation Solution
A receiver circuit with a built-in deterministic latency controller automatically detects and stores the worst-case latency and a link reinitialization compensation offset, computing a golden reference release latency to ensure deterministic latency without manual user intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual latency measurement procedures are used, then deterministic latency can be verified, but the time and cost required increase significantly
Solution Approach 1:
The system performs self-measurement of latency characteristics through automated counters and timing logic built into the receiver block, eliminating the need for external manual measurement tools and procedures
Solution Approach 2:
The latency counter and timing logic are pre-configured and ready to automatically measure latency at the moment of link reinitialization, capturing the worst-case latency before any manual intervention is needed
2Measurement precision
If multiple system reinitializations are performed to measure worst-case latency, then accurate deterministic latency can be obtained, but the complexity of the procedure increases
Solution Approach 1:
The latency counter provides automatic feedback about the measured latency value, and the system uses this feedback to determine when the worst-case latency has been captured, eliminating the need for complex external measurement procedures
Solution Approach 2:
The latency counter and timing logic act as intermediaries between the link reinitialization event and the worst-case latency determination, automatically capturing and reporting the measurement without requiring external measurement equipment
3Reliability
If latency is measured across various process corners, then comprehensive deterministic latency verification is achieved, but the time and resource requirements increase
Solution Approach 1:
The latency measurement mechanism is designed to be universal and automatically adapt to different process corners and operating conditions, eliminating the need for separate measurement procedures for each corner
Data Source
AI summary
A transmitter device may communicate with a receiver device via one or more data links. Data transmitted over the data links may be conveyed in accordance with a communications protocol that requires a deterministic latency for all data lanes in each of the data links. The receiver device may include a deterministic latency controller configured to store a worst-case latency value acquired upon initial startup and a predetermined link reinitialization latency compensation value. During normal operation, the deterministic latency controller may sum together the worst-case latency value and the predetermined link reinitialization latency compensation value to obtain a total compensated deterministic latency that is applied to all data links for simultaneous data release.