Deterministic Built-In Self-Test Using Test Vector Memory
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Solution Overview
Problem
Current testing methods for integrated circuits (ICs) lack comprehensive and deterministic fault detection, leading to incomplete coverage of potential defects and inefficiencies in the testing process.
Innovation Solution
A deterministic built-in self-test (DBIST) architecture that includes a test vector memory (TVM) space and a DBIST direct memory access (DMA) controller to apply predetermined test patterns directly to hardware blocks, ensuring exhaustive fault coverage through a systematic testing methodology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional random testing approaches are used, then the testing process is simpler to implement, but fault coverage is incomplete and non-deterministic
Solution Approach 1:
Test patterns are pre-generated and stored in TVM memory before the actual testing process. The DBIST controller retrieves these predetermined patterns from memory and applies them systematically to the hardware block under test, ensuring comprehensive fault coverage without requiring complex real-time pattern generation logic.
2Reliability
If comprehensive test patterns are applied to all hardware blocks, then fault detection coverage is maximized, but test time increases significantly
Solution Approach 1:
The system segments the testing process by dividing hardware blocks into groups and applying different test patterns from the TVM memory to different segments. The DBIST controller can selectively apply subsets of test patterns to specific hardware blocks based on their type and criticality, enabling parallel testing and reducing overall test time while maintaining comprehensive coverage.
3Measurement precision
If a dedicated testing infrastructure is built for each hardware block, then testing accuracy is maximized, but hardware cost increases
Solution Approach 1:
The DBIST controller serves as a universal testing device that can test multiple different hardware blocks using a single unit. The controller retrieves appropriate test patterns from the shared TVM memory and applies them to various hardware blocks, eliminating the need for dedicated testing infrastructure for each block while maintaining high testing accuracy through deterministic pattern application.
Data Source
AI summary
Embodiments herein describe a computer architecture including a device having a test vector memory (TVM) space configured to store test patterns and a deterministic built-in self-test (DBIST) direct memory access (DMA) controller configured to receive the test patterns directly from the TVM space and apply the test patterns to at least one hardware block under test. The DBIST DMA controller sends a scan bus signal and a scan clock signal to the at least one hardware block under test, the scan bus signal providing the test patterns to the at least one hardware block under test. The test patterns are generated by a manufacturer of the at least one hardware block under test.