Deterministic Trading Architecture for Low-Latency Order Processing
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Solution Overview
Problem
Current electronic trading systems face challenges in maintaining transactional determinism, especially under high loads, due to clock drift and increased transaction volumes, which can lead to non-deterministic behavior and unfair access to information, compromising the system's ability to process orders in a predictable and fair manner.
Innovation Solution
The implementation of a deterministic architecture using redundant match engines and a sequencer that augments transactions with time signal data, ensuring ordered processing and fault-tolerant operation, while using FPGA-based systems to avoid unnecessary optimizations and improve performance by collocating components and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single system component is used to process operations sequentially and replicate state to redundant components, then transactional determinism and fault tolerance are improved, but system throughput is limited by the processing speed of the single component
Solution Approach 1:
The system segments the processing architecture into a coordinator component that maintains determinism and multiple worker components that execute operations in parallel. The coordinator sequences operations and distributes them to multiple workers, allowing throughput to scale with the number of workers while the coordinator ensures transactional determinism by controlling the execution order.
Solution Approach 2:
A coordinator component acts as an intermediary between the need for deterministic processing and parallel execution. It receives operations, assigns sequence numbers, and distributes them to worker components, thereby mediating between the requirements for transactional determinism and high throughput without requiring a single bottleneck component.
2Measurement precision
If clock synchronization protocols are used to compensate for drift, then time-based coordination between components is improved, but processing latency increases due to synchronization overhead
Solution Approach 1:
The system performs preliminary sequencing of operations at the coordinator before distribution to workers. By assigning sequence numbers in advance and using these as the primary coordination mechanism, the system eliminates the need for continuous clock synchronization during processing, thereby reducing latency while maintaining coordination precision.
Solution Approach 2:
The system replaces the mechanical clock synchronization approach with a logical sequencing mechanism. Instead of relying on synchronized physical clocks, the coordinator assigns logical sequence numbers to operations, and workers execute based on these logical timestamps, substituting a software-based logical system for hardware-based time synchronization.
3Productivity
If multiple processing components operate in parallel, then system throughput is improved, but maintaining the same processing order across components becomes difficult due to clock drift
Solution Approach 1:
The system segments processing into coordination (sequence assignment) and execution (parallel processing). The coordinator handles sequencing while workers handle parallel execution, allowing throughput to increase with more workers while the coordinator maintains processing order consistency through logical sequencing.
Solution Approach 2:
The coordinator serves as an intermediary that establishes the processing order before parallel execution begins. It assigns sequence numbers to operations and distributes them to multiple workers, ensuring that even though workers execute in parallel, they all follow the same logical sequence, thereby maintaining processing order consistency across parallel components.
Data Source
AI summary
The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that process or execute instructions. The instructions are sent to the transaction processors before they are to be executed, so that when an instruction identifier corresponding to a pre-sent or pre-loaded instruction is sent to a transaction processor, the transaction processor can retrieve and execute the corresponding instruction without unnecessary delay, thus reducing transaction processing latency and improving computing efficiency.