Deuterated Gate Cap for Charge Trap Memory Reliability
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Solution Overview
Problem
Conventional methods for passivating non-volatile charge trap memory devices, such as SONOS devices, face challenges due to the need for high-temperature deuterium anneals, which are hazardous and increase the thermal budget, and are limited by deuterium's inability to diffuse through nitride layers, affecting device reliability and data retention.
Innovation Solution
Incorporating deuterium into the gate stack and sidewall spacers of semiconductor devices during deposition using deuterated precursor gases like ND3 and SiD4, allowing for deuterium to diffuse and passivate interface traps at lower temperatures, thereby enhancing device reliability and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deuterium anneal is performed at high temperature (500-700°C) for extended duration (4-5 hours), then interface traps are passivated, but thermal budget increases and device functionality degrades
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature annealing (500-700°C) to low-temperature processing (room temperature to 400°C). This is achieved by incorporating deuterium during the deposition process itself rather than through subsequent thermal annealing, fundamentally altering the temperature regime required for effective passivation.
Solution Approach 2:
The patent performs deuterium incorporation during the deposition process itself, before the device is completed and before any annealing steps. This preliminary action embeds the passivating deuterium atoms directly into the nitride layer and interfaces during fabrication, eliminating the need for separate high-temperature annealing steps.
2Reliability
If deuterium anneal is performed, then interface traps are passivated, but processing time increases to 4-5 hours
Solution Approach 1:
The patent performs deuterium incorporation during the deposition process itself, before the device is completed and before any annealing steps. This preliminary action embeds the passivating deuterium atoms directly into the nitride layer and interfaces during fabrication, eliminating the need for separate high-temperature annealing steps.
Solution Approach 2:
The patent merges the deuterium passivation function with the existing deposition process. Instead of performing deuterium annealing as a separate post-processing step, the deuterium incorporation is combined with the nitride layer deposition, reducing total process time and steps.
3Reliability
If pure hydrogen or deuterium is used for annealing, then passivation is achieved, but safety hazards increase
Solution Approach 1:
The patent performs deuterium incorporation during the deposition process itself, before the device is completed and before any annealing steps. This preliminary action embeds the passivating deuterium atoms directly into the nitride layer and interfaces during fabrication, eliminating the need for separate high-temperature annealing steps.
Solution Approach 2:
The patent uses deuterated precursor gases (such as deuterated silane or deuterated ammonia) as intermediaries to deliver deuterium during deposition. These precursor gases allow controlled incorporation of deuterium into the growing nitride layer without requiring the use of pure molecular deuterium or hydrogen, thereby reducing safety hazards associated with handling pure hydrogen or deuterium gases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data retention and reduces the thermal budget required for passivation, providing a safer and more effective method for enhancing the long-term reliability of non-volatile memory devices by using deuterium as a passivating agent within the device layers rather than relying on external anneals.
Implementation Method 1
allowing for deuterium to diffuse and passivate interface traps at lower temperatures
Implementation Method 2
Incorporating deuterium into the gate stack and sidewall spacers of semiconductor devices during deposition using deuterated precursor gases like ND3 and SiD4
Implementation Method 3
the dangling bonds within an oxide-silicon interface may be bonded to atomic hydrogen (H) or deuterium (D), removing the interface trap
Data Source
AI summary
Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a higher deuterium concentration at an interface with the gate layer than at surface of the gate cap layer distal from the gate layer. In certain embodiments, the channel comprises polysilicon or recrystallized polysilicon. Other embodiments are also described.