Deuterium Passivation for Non-Planar Transistor Interface Stability
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Solution Overview
Problem
Non-planar transistors, such as finFETs, face issues with impurities and defects at the interface of the gate stack and conductive channel, leading to instability and performance degradation due to high-density interface states and the difficulty in passivating these interfaces, especially as gate dielectric layers thin.
Innovation Solution
Deuterium-based passivation techniques are employed, involving annealing at various temperatures, pressures, and times in a deuterium atmosphere to penetrate the integrated circuit structure and form stable silicon-deuterium bonds, reducing interface charge and stabilizing the transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate dielectric layers are thinned to improve transistor scaling, then device density and performance are improved, but interface defects and impurities increase leading to higher off-state leakage and instability
Solution Approach 1:
The patent changes the chemical composition parameter by using deuterium (D) instead of hydrogen (H) for passivation. Deuterium has different bonding characteristics and lower solubility in silicon compared to hydrogen, which allows it to effectively passivate interface defects while remaining stable and not causing the same reliability issues that plague thinned gate dielectric structures.
Solution Approach 2:
Deuterium acts as an intermediary substance that mediates between the gate dielectric interface defects and the bulk material. It bonds to dangling bonds and impurities at the interface, forming stable silicon-deuterium bonds that reduce off-state leakage without requiring thick gate dielectric layers, thus resolving the contradiction between thinning for density and maintaining stability.
2Reliability
If conventional hydrogen-based passivation is used, then interface defects are reduced, but deuterium provides superior passivation with lower off-state leakage and enhanced stability
Solution Approach 1:
The patent modifies the passivation approach by changing from hydrogen to deuterium. This parameter change exploits the isotopic difference where deuterium's heavier mass and stronger bonding to silicon create more stable passivation with lower off-state leakage. The deuterium annealing process, while requiring controlled atmosphere, integrates into existing CMOS fabrication flows without fundamentally changing manufacturing complexity.
3Manufacturing precision
If deuterium annealing is performed at high pressure, then deuterium penetration and passivation effectiveness are improved, but process complexity and equipment requirements increase
Solution Approach 1:
The patent utilizes pressure as a controllable parameter to enhance deuterium penetration into the semiconductor structure. By performing annealing at elevated pressures (e.g., 1-10 atm or higher), deuterium gas concentration at the interface is increased, improving passivation effectiveness. This parameter adjustment balances the need for effective passivation with reasonable process equipment requirements, as high-pressure annealing chambers are standard in semiconductor manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deuterium passivation effectively minimizes off-state leakage and parasitic capacitance, enhances transistor reliability, and is applicable to various non-planar transistor configurations, including finFETs, nanowire, and vertical channel transistors, even in highly scaled devices with thin gate dielectrics.
Implementation Method 1
annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium
Implementation Method 2
annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium
Data Source
AI summary
Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.