Deuterium Treatment for High-K Transistor Interface Strain
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Solution Overview
Problem
The use of tensile strain producing liners in integrated circuit structures, particularly in PFETs with silicon germanium channel regions, leads to channel interface quality issues with high-K dielectrics, necessitating separate straining layers for NFETs and PFETs, increasing complexity and processing steps.
Innovation Solution
The implementation of a high-pressure deuterium treatment process in conjunction with a single tensile stress-producing layer applied to both NFETs and PFETs, utilizing deuterium regions between the channel regions and gate insulators to improve interface quality, thereby simplifying the structure and reducing processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a tensile strain producing liner is used with silicon germanium channel regions in PFETs, then transistor performance is improved, but channel interface quality deteriorates
Solution Approach 1:
A deuterium-containing layer is introduced as an intermediary between the silicon germanium channel region and the tensile strain producing liner. This intermediary layer mitigates the harmful interaction between the tensile stress and the high-K dielectric interface, allowing the tensile liner to improve transistor performance without degrading channel interface quality.
2Reliability
If separate straining layers are used for NFETs and PFETs to maintain interface quality, then channel interface quality is preserved, but device complexity increases
Solution Approach 1:
The deuterium-containing layer serves as a universal solution that can be applied to both NFETs and PFETs simultaneously. This single layer provides the necessary interface protection for both transistor types, eliminating the need for separate straining layer configurations and reducing overall device complexity.
3Reliability
If separate straining layers are used for NFETs and PFETs, then interface quality is maintained, but processing steps increase
Solution Approach 1:
The deuterium-containing layer is formed as a single unified structure that serves both NFET and PFET regions. By merging the interface protection function into one layer rather than requiring separate layers for each transistor type, the number of processing steps is reduced and manufacturing efficiency is improved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates channel/high-K dielectric interface quality problems in PFETs, allowing a single tensile stress-producing liner to be used for both types of transistors, enhancing transistor performance without inducing gate-induced drain leakage.
Implementation Method 1
heats the substrate in a pressurized vessel containing deuterium to simultaneously form deuterium regions between the complementary channel regions and the gate insulators
Implementation Method 2
heats the substrate in a pressurized vessel containing deuterium
Implementation Method 3
heats the substrate in a pressurized vessel containing deuterium
Data Source
AI summary
An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.