Device Core Failure Detection Through TDM Test Data

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Solution Overview

Problem

Existing test systems struggle to efficiently identify failures in device cores and manage storage of data from cores that have exceeded a predetermined number of failures, leading to inefficiencies in capture memory usage and potential masking of core failures.

Innovation Solution

A system that employs time-division-multiplexed data transmission and analysis to determine fail counts per core, allowing for limited storage of measurement data based on predetermined thresholds and masking of data from failing cores, thereby optimizing memory usage and identifying core failures accurately.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If measurement data from all cores is stored in capture memory, then complete diagnostic information is preserved, but memory capacity is quickly exhausted by data from failing cores

Engineering Contradiction:
Improvediagnostic accuracyVSAvoidmemory capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the measurement data storage by creating separate fail count trackers for each core. This allows the system to monitor and manage memory usage per-core rather than treating all data uniformly, enabling selective retention of data from passing cores while identifying failing cores that consume excessive memory resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of data retention by introducing a dynamic fail count threshold. When a core's fail count exceeds this threshold, its measurement data is no longer stored in capture memory, thereby changing the storage behavior from universal retention to selective retention based on performance parameters.

Inventive Principle:
Principle #35Parameter changes

2Loss of information

If data from all cores is continuously stored, then no diagnostic information is lost, but memory efficiency decreases due to redundant data from failing cores

Engineering Contradiction:
Improvediagnostic informationVSAvoidmemory efficiency
Core Design Contradiction:
Loss of informationVSLoss of energy

Solution Approach 1:

The system performs preliminary analysis by comparing measurement data against expected values in real-time and maintaining fail count records before memory overflow occurs. This preliminary tracking allows the system to proactively identify failing cores and prevent their data from consuming valuable memory capacity, rather than reacting after memory is exhausted.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If the system tracks fail counts for each core, then accurate failure identification is achieved, but system complexity increases

Engineering Contradiction:
Improvefailure detection accuracyVSAvoiddata management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The fail count mechanism serves multiple functions simultaneously: it tracks the number of failures per core, determines when to stop storing data from specific cores, and provides diagnostic information about core reliability. This multi-functionality reduces the need for separate mechanisms for each task, thereby limiting the increase in system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12461141B2Identifying failures in device cores
Publication Date: 2025.11.04 TERADYNE INC
  • US12461141B2 patent drawing
  • US12461141B2 patent drawing
  • US12461141B2 patent drawing

AI summary

An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.