Device Die Trench Layout for Low-Delamination Singulation
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Solution Overview
Problem
As semiconductor dies become smaller and more functions are integrated, the packaging of these dies becomes increasingly difficult due to the rising density of I/O pads, which adversely affects the packaging yield.
Innovation Solution
The method involves forming first and second trenches in the dielectric layer and the passivation layer, respectively, to facilitate the singulation of semiconductor dies using a laser with lower energy density, thereby reducing delamination and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser grooving is performed on wafers with high I/O pad density, then packaging yield deteriorates due to delamination, but reducing laser energy density improves manufacturing precision
Solution Approach 1:
The method forms openings in the dielectric layer before performing laser grooving. This preliminary action creates a protective structure that prevents delamination during subsequent laser processing, allowing high-energy density laser grooving without compromising packaging yield while maintaining groove formation precision
Solution Approach 2:
The dielectric layer is segmented by forming openings that expose portions of the passivation layer. This segmentation allows the laser energy to be confined to specific regions, preventing unwanted delamination in protected areas while enabling precise groove formation in exposed areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient packaging of semiconductor dies by reducing the risk of delamination and improving the yield of the packaging process, even as the density of I/O pads increases.
Implementation Method 1
performing a grooving process to form a second trench in the wafer
Data Source
AI summary
A package including a device die and an encapsulant is provided. The device die includes a semiconductor substrate, an interconnect structure, a conductive via, and a dielectric layer. The interconnect structure is disposed over the semiconductor substrate. The conductive via is disposed over and electrically coupled to the interconnect structure. The dielectric layer is disposed over the interconnect structure and laterally encapsulating the conductive via, wherein the dielectric layer includes a sidewall and a bottom surface facing the interconnect structure, and the sidewall of the dielectric layer is tilted with respect to the bottom surface of the dielectric layer. The encapsulant laterally encapsulates the device die.