Device Directed Memory Barriers for Bus Interconnects
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Solution Overview
Problem
In processing systems, synchronization of bus transactions between multiple bus masters and shared memory devices is inefficient, leading to potential data corruption and increased power consumption due to the need for broadcasted memory barrier commands that require arbitration and response from all slave devices.
Innovation Solution
Implementing a device-directed memory barrier command that provides device-specific information, allowing the bus interconnect to selectively route memory barrier commands to specific destination devices, reducing the need for broadcast operations and optimizing synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadcast memory barrier commands are used to synchronize all slave devices, then data consistency is maintained, but power consumption increases and performance decreases due to arbitration and response requirements from all devices
Solution Approach 1:
The patent segments the memory barrier command targeting by introducing device-directed addressing. Instead of broadcasting to all slave devices, the memory barrier command is segmented to target only the specific slave device identified by the device identifier in the command address field. This segmentation allows selective synchronization, reducing power consumption while maintaining data consistency for the specific device involved in the transaction.
2Reliability
If broadcast memory barrier commands are used to synchronize all slave devices, then data consistency is maintained, but system performance decreases due to arbitration and response overhead from all devices
Solution Approach 1:
The patent segments the memory barrier command targeting by introducing device-directed addressing. Instead of broadcasting to all slave devices, the memory barrier command is segmented to target only the specific slave device identified by the device identifier in the command address field. This segmentation eliminates unnecessary arbitration and response overhead from devices not involved in the transaction, improving system performance while maintaining data consistency.
3Use of energy by moving object
If selective routing of memory barrier commands is implemented, then power consumption and arbitration overhead are reduced, but device complexity increases due to decoding and routing logic
Solution Approach 1:
The patent applies preliminary action by pre-configuring the interconnect with device identifier routing logic. The interconnect is designed to automatically decode the device identifier from the command address field and route the memory barrier command to the appropriate slave device before the command is executed. This preliminary routing setup reduces the need for complex runtime arbitration and decoding logic, balancing the trade-off between selectivity and device complexity.
4Reliability
If traditional memory barrier broadcasting is used, then synchronization is ensured across all devices, but unnecessary acknowledgments are generated from devices not involved in the transaction
Solution Approach 1:
The patent segments the memory barrier command targeting by introducing device-directed addressing. The command includes a device identifier that is decoded by the interconnect to determine the specific slave device target. This segmentation ensures that only the relevant device generates an acknowledgment, eliminating unnecessary acknowledgments from devices not involved in the transaction while maintaining proper synchronization for the affected device.
Data Source
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AI summary
Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.