Device Layer Interconnect Layout for Low-Capacitance 3D IC Routing
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Solution Overview
Problem
Conventional approaches to electrically coupling device layers in integrated circuits (ICs) result in significant area penalties and undesirable electrical performance, such as excessive capacitive coupling, which limits signaling speed.
Innovation Solution
The development of device layer interconnects that extend through the device layer to provide a conductive connection between frontside and backside interconnects in 3D ICs, using a trench filled with metal and formed in a gate region of a dummy transistor, enabling high-density and low-capacitance signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches are used to electrically couple device layers, then electrical connection is achieved, but area penalty increases and capacitive coupling becomes excessive
Solution Approach 1:
The patent transitions from planar coupling within a single device layer to three-dimensional coupling by extending the interconnect through the device layer to reach both frontside and backside interconnects, utilizing the vertical dimension to reduce lateral area requirements
Solution Approach 2:
The device layer interconnect is formed within a gate region of a dummy transistor, nesting the interconnect structure within an existing transistor footprint rather than requiring separate dedicated coupling structures
2Reliability
If conventional approaches are used to electrically couple device layers, then electrical connection is achieved, but capacitive coupling becomes excessive limiting signaling speed
Solution Approach 1:
The patent extracts the harmful capacitive coupling by removing the intermediate coupling structures and direct lateral connections that cause excessive capacitance, replacing them with a through-layer vertical interconnect that minimizes parasitic effects
Solution Approach 2:
The device layer interconnect acts as an intermediary structure that provides a low-capacitance pathway through the device layer, mediating the electrical connection between frontside and backside interconnects while minimizing harmful capacitive effects
3Area of stationary object
If device layer interconnects are formed in gate regions of dummy transistors, then area efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The gate region of the dummy transistor serves multiple functions: it provides the structural framework for the transistor itself and simultaneously serves as the template and containment structure for the device layer interconnect, eliminating the need for separate interconnect formation steps
Solution Approach 2:
The patent merges the interconnect formation process with the existing transistor fabrication process, combining what would traditionally be separate steps into a unified flow that reduces overall manufacturing complexity despite the innovative structure
Data Source
Figure 1A
Figure 1B~1C
Figure 2A
AI summary
Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.