Hybrid-Paging With a Device-Side Page Presence Table
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Solution Overview
Problem
Existing memory management systems face inefficiencies in handling data access across multiple memory locations, particularly in systems with tiered memory configurations, due to the need for complex table walks and cache coherency mechanisms, which can lead to performance bottlenecks and resource utilization issues.
Innovation Solution
A hybrid-paging (HPG) system that offloads address translation to an expansion device using a device-side page presence table (PPT), allowing host devices to access data without table walks and optimizing resource usage by managing high-latency tiered-memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex table walks and cache coherency mechanisms are used in existing memory management systems, then data access across multiple memory locations can be handled, but performance bottlenecks and resource utilization issues occur
Solution Approach 1:
The patent extracts the page presence determination function from the host device and implements it in the expansion device. The expansion device maintains a page presence table (PPT) that directly indicates which memory pages are present in its memory, eliminating the need for the host to perform complex table walks through page tables. This extraction of the paging management function to the expansion device resolves the contradiction by maintaining data access correctness while dramatically improving performance.
Solution Approach 2:
The patent introduces a page presence table (PPT) as an intermediary data structure that sits between the host's virtual address space and the expansion device's physical memory. The PPT provides a direct mapping from virtual page numbers to presence status, acting as a mediator that simplifies the address translation process. This intermediary structure eliminates the need for multi-level page table walks while ensuring correct data access, thus resolving the performance bottleneck.
2Adaptability or versatility
If traditional memory paging is used with page tables, then virtual memory management can be implemented, but complex address translation and cache coherency management are required
Solution Approach 1:
The patent inverts the traditional paging architecture by placing the page presence table in the expansion device rather than in the host. Instead of the host maintaining page tables and managing paging for the expansion device's memory, the expansion device autonomously maintains its own PPT and manages its memory paging independently. This inversion simplifies the host's address translation complexity while preserving full virtual memory management capability.
Solution Approach 2:
The patent segments the memory management functions by separating the host's virtual address space management from the expansion device's physical memory management. The expansion device independently manages its own memory pages using a local PPT, while the host manages its virtual address space. This segmentation of paging responsibilities eliminates the need for complex coordinated address translation between host and expansion device.
3Reliability
If the host device performs all address translation and paging management, then complete control over memory can be maintained, but computational load and performance degradation occur
Solution Approach 1:
The patent enables the expansion device to serve itself by implementing autonomous paging management. The expansion device maintains its own page presence table and independently determines which memory pages are present, eliminating the need for the host to perform address translation and paging management for the expansion device's memory. This self-service approach maintains memory control accuracy while significantly reducing the host's computational load and energy consumption.
Data Source
AI summary
Examples are disclosed herein relating to memory paging. In some examples, a host device is configured to communicate with an expansion device. The expansion device can include first and second memory, and a device virtual memory address (DVA) table. The expansion device can store data that can be requested by the host device. The first memory is a cache for the second memory based on a page presence table (PPT). The PPT can indicate a presence of second memory pages in the first memory cache. The DVA table can include information to locate data in the first memory based on a host physical memory address of a memory request. The device physical memory address can identify a memory location at which the data is stored. The data can be provided from the expansion device to the host device in response to the memory request based on the PPT.