Device Variation Extraction Chip for Semiconductor Mismatch Measurement

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional methods for measuring device variation and mismatch in semiconductor manufacturing require extensive resources, large layout areas, and significant test time, making it inefficient to obtain accurate data for improving process technologies and reducing chip failures.

Innovation Solution

A device variation extraction chip design utilizing a 2n-pad test key that connects multiple MOS devices to measure electrical properties and calculate device mismatch, allowing for high-accuracy data collection in a reduced chip area and time, without additional photomask or process steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional test keys with limited pads are used to measure device variation, then the layout area and test time are reduced, but the quantity of measurable devices and data amount are insufficient

Engineering Contradiction:

Improvequantity of measurable devicesVSAvoidlayout area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent merges multiple device measurements into a single test key structure. By sharing common pads (drain, source, gate, bulk) across multiple MOS devices, the test key can measure electrical properties of multiple devices simultaneously without requiring separate test structures for each device, thereby increasing the quantity of measurable devices while controlling layout area

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The test key is designed with multi-functional pads that can serve multiple devices. Each pad (drain, source, gate, bulk) is configured to be shared across different MOS devices, allowing the same physical structure to perform multiple measurement functions and accommodate a larger number of devices

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If conventional test keys with limited pads are used, then the chip area is reduced, but the test time increases due to insufficient data collection capability

Engineering Contradiction:

Improvetest timeVSAvoidchip area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

Multiple device measurements are merged into a single test key structure, enabling parallel measurement of multiple devices simultaneously. This reduces the total test time by eliminating sequential measurement requirements while maintaining a compact chip area through shared pad architecture

Inventive Principle:

Principle #5Merging (Combining)

3Measurement precision

If two adjacent identical devices are used as pairs for device mismatch measurement, then the measurement precision is improved, but the number of pads required increases significantly

Engineering Contradiction:

Improvedevice mismatch measurement precisionVSAvoidnumber of pads required

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the pad requirements for multiple device pairs into a shared pad structure. By configuring the test key to share drain, source, gate, and bulk pads across different device pairs, the system can measure multiple pairs simultaneously without requiring separate dedicated pads for each pair, thereby reducing overall pad count while maintaining measurement precision

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The test key pads are designed with universal functionality to serve multiple device pairs. Each pad is configured to accommodate multiple devices through sharing, allowing the same physical pads to be used for measuring different device pairs and their mismatches without increasing the total pad requirement

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Measurement precision

If a large amount of device data is measured to determine device behavior and process impacts, then the measurement precision is improved, but the resources and test time required increase significantly

Engineering Contradiction:

Improvedevice variation measurement precisionVSAvoidtest time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

Multiple device measurements are merged into a single integrated test key that can collect data from multiple devices in parallel. This enables the acquisition of a large amount of device data without proportionally increasing test time, as multiple measurements occur simultaneously rather than sequentially

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The test key is pre-configured with shared pad structures and connection arrangements that enable simultaneous measurement of multiple devices. This preliminary setup allows for efficient data collection from the start of testing, reducing the overall test time required to gather sufficient device variation data

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250102556A1Device variation extraction chip

Publication Date: 2025.03.27 SHANGHAI HUALI INTEGRATED CIRCUIT CORP

AI summary

The present application discloses a device variation extraction chip, including m MOS devices and one test key, where the test key has 2n pads; a drain of the (k(n−1)+i)-th MOS device is short-circuited with the i-th pad of the test key; a gate of the (k(n−1)+i)-th MOS device is short-circuited with the (n−1+i)-th pad of the test key; a source of each of the m MOS devices is short-circuited with the (2n−1)-th pad; a bulk of each of the m MOS devices is short-circuited with the 2n-th pad. The device variation extraction chip can save the chip area, save the test time, obtain a large amount of data, and improve the accuracy of the obtained device variation and device mismatch, without the addition of a photomask and process node steps.