DevPIC Cache for PCIe ATS LAM SVM Coexistence

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Solution Overview

Problem

Existing technologies face inefficiencies in storing process-specific information in devices that support Address Translation Service (ATS) of a PCIe architecture, particularly in combining Linear Address Masking (LAM) and Shared Virtual Memory (SVM) without mutual exclusivity.

Innovation Solution

The implementation of a Device ProcessInfoCache (DevPIC) within devices that support ATS, which allows for the storage of process-specific information, including linear address masks and domain IDs, enabling the coexistence and efficient use of LAM and SVM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If LAM and SVM are implemented as mutually exclusive features, then system complexity is reduced and ease of operation is improved, but adaptability and versatility deteriorate because users cannot use both features together

Engineering Contradiction:

Improveease of operationVSAvoidadaptability

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent merges LAM and SVM functionalities by introducing a DevPIC (Device Process Info Cache) that stores process-specific information including linear address masks. This allows both LAM and SVM to coexist and operate simultaneously within the same system, resolving the mutual exclusivity constraint while maintaining operational simplicity through unified cache management.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The DevPIC structure is designed to be universal, supporting both LAM and SVM operations through a single cache mechanism. The cache can store and retrieve process-specific information for different address translation scenarios, making the system adaptable to multiple features without requiring separate specialized structures for each feature.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If process-specific information is stored in device caches, then productivity and speed are improved by reducing latency in invalidating DevTLBs, but device complexity increases

Engineering Contradiction:

ImproveproductivityVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The DevPIC is implemented as a nested cache structure within the device, where process-specific information is stored in a compact format alongside existing DevTLB structures. This nesting approach minimizes the additional complexity by reusing existing cache infrastructure and management protocols, while still providing the productivity benefits of reduced invalidation latency.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Adaptability or versatility

If a software-based solution is used to perform address masking, then adaptability is improved, but productivity deteriorates due to high computational overhead and latency

Engineering Contradiction:

ImproveadaptabilityVSAvoidproductivity

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces the software-based address masking mechanism with a hardware-based DevPIC that performs masking operations in parallel with memory access. This substitution eliminates the sequential software processing overhead while maintaining the adaptability of dynamic address masking, thereby significantly improving productivity without sacrificing versatility.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12222873B2Method and apparatus to enable a cache (DEVPIC) to store process specific information inside devices that support address translation service (ATS)

Publication Date: 2025.02.11 INTEL CORP

AI summary

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to PCIe Address Translation Service (ATS) to allow devices to have a DevTLB that caches address translation (per page) information in conjunction with a Device ProcessInfoCache (DevPIC) that will store process specific information. Other embodiments may be described and/or claimed.