DFA Graph Caching via Accessibility Ranking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current networking systems face performance limitations in processing high-level network protocols (L4-L7) at wire-speed, particularly in content-aware applications like Intrusion Detection Systems, due to insufficient processing capabilities of general-purpose processors.
Innovation Solution
A processor is designed to efficiently store and retrieve portions of a Deterministic Finite Automata (DFA) graph by caching cacheable portions based on accessibility rankings, reducing external memory accesses and optimizing node structures for faster content searches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general purpose processor is used to process L4-L7 network protocols, then intelligent processing capability is improved, but processing speed deteriorates and cannot achieve wire-speed forwarding
Solution Approach 1:
The DFA graph is segmented into cacheable portions (frequently accessed nodes) and non-cacheable portions. The processor separates hot nodes that benefit from caching and cold nodes that do not, allowing selective optimization without compromising overall processing capability.
Solution Approach 2:
Different storage strategies are applied to different parts of the graph based on accessibility rankings. High-accessibility nodes are cached in fast memory while lower-accessibility nodes remain in main memory, creating local optimization tailored to access patterns.
2Speed
If the entire DFA graph is cached in fast memory, then access speed is improved, but memory resource consumption increases
Solution Approach 1:
The system changes the parameter of memory allocation by using accessibility rankings to determine which nodes deserve fast cache memory. This parameter-based selection optimizes the balance between access speed and memory resource consumption.
Solution Approach 2:
Instead of caching the entire graph (excessive action), the system caches only the necessary portion (partial action) - specifically, nodes with high accessibility rankings. This partial caching achieves most of the performance benefit while consuming fewer resources.
3Productivity
If accessibility ranking is used to select cacheable portions, then cache efficiency is improved, but processing complexity increases
Solution Approach 1:
Accessibility rankings are computed in advance during a compilation stage before the actual graph traversal begins. This preliminary computation eliminates the need for complex real-time analysis during packet processing, reducing runtime complexity.
Solution Approach 2:
The DFA graph structure itself provides the information needed for caching decisions through its inherent node connectivity and accessibility properties. The system leverages the graph's own characteristics rather than requiring external complex analysis.
Data Source
AI summary
In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.