DFA Module Asynchronous Packet Processing
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Solution Overview
Problem
Current networking systems face performance limitations in processing high-level network protocols (L4-L7) and content-aware applications, particularly with compute-intensive tasks like checksum calculation and pattern matching, which require significant post-processing and do not achieve wire-speed performance.
Innovation Solution
A network services processor with a deterministic finite automata (DFA) module operates asynchronously to traverse DFA graphs, utilizing a combination of cached and non-cached memory to accelerate packet processing and content-aware applications, including regular expression matching, by scheduling DFA instructions and issuing memory access instructions for efficient pattern search.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general purpose processor is used to process L4-L7 network protocols, then intelligent processing capability is improved, but processing speed deteriorates and cannot achieve wire-speed performance
Solution Approach 1:
The system segments processing tasks by separating L2-L3 packet forwarding functions (handled by network processors for high speed) from L4-L7 protocol processing functions (handled by general purpose processors for intelligence). This segmentation allows each component to operate at its optimal performance level without compromising the other.
Solution Approach 2:
A communication interface acts as an intermediary between the network processor and the general purpose processor, enabling efficient data transfer and coordination. This intermediary facilitates the exchange of packet data and processing results, allowing the system to achieve both high speed and intelligent processing capability.
2Measurement precision
If DFA search algorithm is used for content processing, then pattern matching capability is improved, but graph size grows exponentially and false matches increase
Solution Approach 1:
The system changes the representation parameters of the DFA graph by storing it in a database with optimized data structures. This transformation reduces the memory footprint and improves access efficiency, allowing the system to handle large-scale pattern matching without exponential graph growth.
Solution Approach 2:
The patent replaces the traditional in-memory DFA graph structure with a database-based storage system. This substitution enables efficient pattern matching capability while avoiding the exponential growth of graph size in memory, as the database can store and manage large graphs with optimized storage schemes.
3Measurement precision
If content processing applications examine packet content, then pattern search capability is improved, but post processing requirements increase significantly
Solution Approach 1:
The system performs preliminary actions by pre-compiling regular expressions into DFA graphs and storing them in the database before actual pattern matching operations. This preliminary preparation reduces the complexity of post-processing by having the pattern matching results ready in an optimized format that requires minimal additional processing.
Data Source
AI summary
A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.