DFE Amplifier Gain Characterization via Test Pattern BER
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Solution Overview
Problem
Characterizing the gain of amplifiers within a decision feedback equalizer (DFE) embedded in a custom integrated circuit (ASIC) is challenging due to the lack of direct access to internal analog output voltages and gain input voltages, complicating the measurement and qualification of ASIC parts during production.
Innovation Solution
A test generator system that generates a test pattern signal with an offset voltage and a digital command word to determine the amplification level by measuring the bit error rate between the test pattern and the DFE output signal, allowing the determination of amplifier gains without direct observation of internal amplifier outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the DFE is embedded in a custom integrated circuit (ASIC), then the device integration and compactness are improved, but the ease of measuring and characterizing amplifier gains deteriorates due to lack of direct access to internal signals
Solution Approach 1:
The patent introduces a test generator as an intermediary device that interfaces with the embedded DFE through its digital input/output ports. This mediator generates test patterns and measures bit error rates to indirectly characterize the amplifier gains without requiring direct access to internal analog signals, thus resolving the measurement difficulty while preserving the embedded architecture
Solution Approach 2:
The patent replaces the traditional direct electrical measurement approach (mechanical/probe-based access to internal nodes) with a digital signal processing approach. By using digital test patterns and bit error rate measurements, the system substitutes physical probing with digital characterization methods, enabling gain measurement through software-controlled digital interfaces
2Measurement precision
If direct access to internal amplifier outputs is provided for measurement, then the measurement precision is improved, but the device complexity and ease of manufacture deteriorate due to additional access points and routing
Solution Approach 1:
The test generator acts as an intermediary that achieves precise amplifier characterization without adding physical access points to the ASIC. By using the existing digital I/O ports as communication channels and employing sophisticated test algorithms (bit error rate measurement with varying offset voltages), the system obtains precise gain data without modifying the physical structure of the embedded DFE
Solution Approach 2:
The patent creates a digital model or representation of the amplifier behavior through bit error rate measurements rather than directly copying physical access to internal nodes. The test generator captures the functional behavior of the amplifiers by measuring their effect on digital test patterns, creating a virtual characterization that avoids the need for physical access modifications
Data Source
AI summary
A test generator that determines an amplification level of an amplifier within a DFE and a method for determining the amplification level are disclosed. The test generator includes a signal generator that generates a test pattern signal characterized by a repeating digital test pattern and an offset voltage and an input signal port adapted to receive a digital DFE output signal from the DFE, the digital DFE output signal depending on the amplification level. The test generator includes an output control port that communicates a digital command word specifying a gain to be used by the amplifier in the DFE and a threshold for determining if a signal in the DFE is a logical one or logical zero. A controller determines the amplification level by measuring a BER between the test pattern and the digital DFE output signal as a function of the threshold and the offset voltage.