Decision Feedback Equalizer Calibration for Variable Serial Data Rates
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Solution Overview
Problem
Feedback equalizers, particularly decision feedback equalizers (DFEs) in semiconductor devices, face challenges in properly equalizing serial data at different transfer rates due to variations in delay time, leading to inadequate waveform shaping and potential erroneous equalization when used across different standards like PCI Express Gen1 to Gen4.
Innovation Solution
A semiconductor device with a feedback equalizer configuration that includes an addition circuit, sampling circuits, multiplication circuits, a tap coefficient determination circuit, and a calibration circuit to adjust delay time and tap coefficients, ensuring proper equalization across varying transfer rates by executing a calibration mode to set optimal delay times and coefficients for each standard.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a DFE is designed for the highest transfer rate (Gen4) and reused for lower rates (Gen1-Gen3), then device complexity and manufacturing cost are reduced, but delay time variation causes improper equalization
Solution Approach 1:
The patent introduces a calibration circuit that dynamically adjusts the delay time of the analog circuit based on the transfer rate. This allows a single DFE configuration to adapt to different transfer rates (Gen1-Gen4) by changing its timing characteristics, thereby maintaining equalization accuracy across all standards while using one unified design.
Solution Approach 2:
The patent changes the delay time parameter of the analog circuit through calibration based on the operating transfer rate. By adjusting this critical parameter, the DFE can properly equalize signals at different speeds without requiring separate hardware designs for each generation standard.
2Reliability
If separate DFEs are designed for each transfer rate standard, then equalization accuracy is maintained, but designing time and manufacture cost increase
Solution Approach 1:
The patent creates a universal DFE design that can function across multiple PCI Express standards (Gen1-Gen4). The calibration circuit enables this single design to serve multiple purposes by adjusting its delay characteristics, eliminating the need to manufacture separate DFEs for each standard and thereby reducing production costs.
Solution Approach 2:
The dynamic delay adjustment capability allows the DFE to adapt to different transfer rate requirements, making a single design suitable for all generations. This dynamic flexibility replaces the need for multiple static designs, simplifying the manufacturing process.
3Speed
If analog circuit delay time is fixed for highest transfer rate, then high-speed equalization is achieved, but delay time becomes insufficient for lower transfer rates
Solution Approach 1:
The calibration circuit dynamically adjusts the delay time based on the detected transfer rate. When operating at Gen4 speeds, the delay is set to the minimum required for high-speed performance. When operating at lower rates (Gen1-Gen3), the delay is increased to match the slower timing requirements, ensuring proper equalization across all standards.
Solution Approach 2:
The patent changes the delay time parameter of the analog circuit according to the operating transfer rate. This parameter adjustment enables the same hardware to optimize performance for both high-speed (Gen4) and lower-speed (Gen1-Gen3) operations.
Data Source
AI summary
The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.