DFE Clock Recovery Using Detected Data for High-Speed Equalization
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Solution Overview
Problem
At high data rates, decision-feedback equalization (DFE) circuits face challenges in designing accurate and fast circuits to operate within one baud period, leading to difficulties in compensating for channel impairments like intersymbol interference, as existing methods rely on precomputing DFE terms without feedback loops, processing unequalized data.
Innovation Solution
The method generates clock signals for a decision-feedback equalizer using DFE detected data by sampling a received signal with both data and transition clocks, applying DFE corrections to these samples, and using a phase detector to adjust the clock signals, enabling effective equalization and data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DFE circuits operate at very high data rates within one baud period, then data recovery speed is improved, but circuit accuracy and reliability deteriorate due to difficulty in designing fast-accurate circuits
Solution Approach 1:
The patent segments the DFE operation into multiple phases: a first phase for processing data samples and a second phase for processing transition samples. This segmentation allows each phase to be optimized independently, with the first phase handling primary data recovery and the second phase refining the equalization using transition information, thereby achieving both high speed and high accuracy at very high data rates
Solution Approach 2:
The patent performs preliminary DFE correction on data samples in the first phase before using those corrected decisions to generate correction terms for transition samples in the second phase. This preliminary action allows the system to prepare equalization corrections in advance, improving overall processing speed while maintaining accuracy through the two-phase approach
2Device complexity
If DFE terms are precomputed without feedback loops, then circuit complexity is reduced and processing speed is improved, but equalization accuracy deteriorates because unequalized data is processed
Solution Approach 1:
The patent implements feedback by using DFE corrected data decisions from the first phase to generate correction terms for transition samples in the second phase. The corrected data decisions are fed back into the system to improve the equalization of transition samples, thereby maintaining accuracy while avoiding the need for complex feedback loops in the traditional sense
Solution Approach 2:
The patent performs preliminary DFE correction on data samples before using those corrections for transition sample processing. This preliminary equalization action improves the quality of data decisions used for generating correction terms, thereby improving overall equalization accuracy without requiring the data to be fully equalized before processing begins
3Device complexity
If a single clock is used for both sampling and DFE operation, then device complexity is reduced, but processing reliability deteriorates at very high data rates
Solution Approach 1:
The patent segments the clocking function into two separate clocks: a data clock for sampling data samples and a transition clock for sampling transition samples. This segmentation allows each clock to be optimized for its specific purpose, with the transition clock potentially operating at different phases or timings to capture transition information more reliably, thereby improving overall system reliability at high data rates
Data Source
AI summary
Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.