Decision Feedback Equalizer Clock Retiming for Multi-Rate Jitter Tolerance
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Solution Overview
Problem
Current decision feedback equalizer (DFE) systems face challenges in maintaining predictable feedback at input summation nodes and are limited to operating at single data rates, with poor jitter tolerance and compatibility issues with varying data rates and signal jitter.
Innovation Solution
The implementation of DFE circuitry that uses delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via DFE taps, ensuring correct feedback signal timing and increased jitter tolerance across a wide range of data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed delay circuitry is used to determine data rate, then reliable operation at a single data rate is achieved, but adaptability to multiple data rates is lost
Solution Approach 1:
The patent applies dynamics by making the delay circuitry adjustable rather than fixed. The delay amount can be dynamically changed based on the detected data rate, allowing the DFE to adapt to different data rates while maintaining reliable operation at each rate through optimized delay settings.
Solution Approach 2:
The patent changes the delay parameter of the circuit based on the detected data rate. By adjusting the delay amount as a variable parameter rather than a fixed value, the system can optimize performance across multiple data rates while maintaining reliability at each specific rate.
2Adaptability or versatility
If variable delay circuitry is used to support multiple data rates, then adaptability is improved, but circuit complexity and timing control difficulties increase
Solution Approach 1:
The patent uses dynamic delay adjustment with a controlled clock signal whose duty cycle varies with data rate. This provides the necessary adaptability for multiple data rates while keeping the circuit implementation relatively simple through systematic clock control rather than complex variable delay mechanisms.
Solution Approach 2:
The controlled clock signal serves multiple functions: it provides timing for the DFE circuitry, its duty cycle indicates the data rate, and it controls the delay amount. This multi-functionality reduces overall circuit complexity by combining several functions into a single clock mechanism.
3Loss of time
If delay is introduced to the clock signal, then timing for feedback signal is improved, but additional delay in the data path is required
Solution Approach 1:
The patent uses a controlled clock signal as an intermediary to transfer timing information. The clock's duty cycle serves as the mediator that conveys data rate information to the delay circuitry, enabling proper timing without requiring direct complex delay control mechanisms.
Solution Approach 2:
The system uses the clock signal itself to provide the timing information needed for delay control. The clock's inherent duty cycle characteristics automatically provide the timing parameters needed, eliminating the need for separate complex timing control circuits.
Data Source
AI summary
Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.