Decision Feedback Equalizer Delay Calibration for Variable Data Rates
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Solution Overview
Problem
Existing decision feedback equalizers (DFEs) face challenges in properly equalizing serial data at different transfer rates, leading to insufficient or erroneous waveform shaping due to constant delay times in analog circuits, which complicates the design and increases manufacturing costs when adapting to various PCI Express standards.
Innovation Solution
A semiconductor device with a DFE that incorporates variable delay circuits and a calibration mode to adjust delay times and tap coefficients, ensuring proper equalization across different transfer rates by synchronizing feedback data addition with the changing clock signal, thereby maintaining waveform integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DFE is designed for the highest transfer rate (Gen4) and used for lower transfer rates (Gen1-Gen3), then the design time and manufacture cost are reduced, but the equalization performance deteriorates due to fixed delay time in analog circuits
Solution Approach 1:
The patent introduces variable delay circuits that can dynamically adjust their delay time based on the transfer rate. The delay time is changed according to the clock signal frequency, allowing the DFE to maintain proper equalization performance across different transfer rates (Gen1-Gen4) while using a single unified design.
Solution Approach 2:
The patent changes the delay time parameter of the analog circuit based on the operating conditions (transfer rate). By adjusting the delay time parameter according to the clock signal frequency, the DFE adapts to different transfer rates while maintaining optimal equalization performance.
2Reliability
If separate DFEs are designed for each transfer rate standard (Gen1-Gen4), then the equalization performance is optimized for each standard, but the design time and manufacture cost increase
Solution Approach 1:
The patent creates a universal DFE design that can function across multiple transfer rate standards (Gen1-Gen4). The variable delay circuits enable a single DFE design to adapt to different clock signal frequencies, eliminating the need for separate DFE designs for each standard while maintaining optimized equalization performance for each.
3Reliability
If separate DFEs are designed for each transfer rate standard (Gen1-Gen4), then the equalization performance is optimized for each standard, but the manufacture cost increases
Solution Approach 1:
The patent creates a universal DFE design that can function across multiple transfer rate standards (Gen1-Gen4). The variable delay circuits enable a single DFE design to adapt to different clock signal frequencies, eliminating the need for separate DFE designs for each standard while maintaining optimized equalization performance for each.
Data Source
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AI summary
The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.