DFE DQS Gating With 1CLK Gap for Write Timing Margin
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accurately interpreting write data due to reflections at DQ pads, which are caused by factors like capacitance and impedance mismatch, leading to reduced reliability and accuracy in decision feedback equalization (DFE) circuits.
Innovation Solution
Implementing a 1CLK DQS gap internally by allowing a non-continuous external DQS signal between consecutive write commands to enable a signal gating event, ensuring proper reset of the DFE buffer by adding a full clock cycle to the timing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a continuous DQS signal is used between consecutive write commands, then data transmission efficiency is improved, but the DFE buffer cannot be properly reset leading to reduced timing margin and increased errors
Solution Approach 1:
The patent introduces a periodic gap (1CLK DQS gap) in the DQS signal between consecutive write commands. This periodic interruption allows the DFE buffer to be properly reset while maintaining otherwise continuous data transmission. The gating circuitry implements this by selectively blocking the DQS signal during the gap period, creating a rhythmic pattern of signal transmission and reset that resolves the contradiction between continuous transmission and buffer reset requirements.
Solution Approach 2:
The patent introduces a gating circuitry as an intermediary component between the DQS signal and the DFE buffer. This intermediary selectively enables or disables the DQS signal based on timing requirements, allowing the buffer to be reset during the gap while maintaining data transmission during normal operation. The gating circuitry mediates between the conflicting requirements of continuous data transmission and periodic buffer reset.
2Measurement precision
If the DFE buffer is reset more frequently to maintain accuracy, then data interpretation accuracy is improved, but timing margin is reduced and complexity increases
Solution Approach 1:
The patent implements preliminary action by resetting the DFE buffer in advance during the 1CLK gap before the next write command begins. This preliminary reset ensures the buffer is in a known state when data transmission resumes, eliminating the need for complex real-time reset control during data transmission. The reset action is performed beforehand during the gap period, simplifying the overall timing control architecture.
3Reliability
If a 1CLK DQS gap is introduced for buffer reset, then timing margin is increased and reliability is improved, but data transmission time is reduced
Solution Approach 1:
The patent applies the skipping principle by introducing a minimal 1CLK gap in the DQS signal sequence. This short skip is just long enough to allow the DFE buffer to be properly reset, but short enough to minimize impact on overall data transmission. The gating circuitry implements this by blocking the DQS signal for exactly one clock cycle, then resuming transmission without further interruptions. This rushed-through approach achieves reliable buffer reset while minimizing time loss.
Data Source
AI summary
A decision feedback equalizer (DFE) circuit may selectively receive a gated data strobe (DQS) signal based on an external DQS signal. The DFE circuit may capture data to store in a buffer responsive to receiving the gated DQS signal. After a write operation, an additional gating event may occur responsive to one or more internal signals. This may effectively delay when the gated DQS signal is received by the DFE circuit. The gated DQS signal may not be received by the DFE circuit until after a reset of the DFE buffer.