DFE Error Correction Using Suspicious Error Head Detection

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Solution Overview

Problem

Existing error detection and correction methods in high-speed data communication systems, such as DFE and MLSD, fail to effectively eliminate both propagated errors and first random errors, leading to inefficiencies and high implementation complexity.

Innovation Solution

A decision-feedback equalizer (DFE) system with a trellis-based error eliminator (TBEE) that performs forward error detection and correction, detecting the head position of suspicious errors and tracking error propagation paths to correct errors using inter-symbol information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Maximum Likelihood Sequence Detection (MLSD) is used to remove ISI, then error correction capability is improved, but implementation complexity and power consumption increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidimplementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error detection and correction process into distinct functional blocks: a decision-feedback equalizer for initial signal processing, an error detection circuit for identifying suspicious error positions, and an error correction circuit for targeted correction. This segmentation avoids the high complexity of MLSD while achieving effective error correction through specialized, simplified sub-components working in sequence.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If 1+D precoding is used to eliminate DFE error propagation, then error propagation is reduced, but additional errors are introduced and first random errors cannot be eliminated

Engineering Contradiction:
Improveerror propagationVSAvoiderror rate
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent employs feedback mechanisms where the error detection circuit continuously monitors the output of the decision circuit, identifies suspicious error positions based on decision reliability, and feeds this information to the error correction circuit. This closed-loop feedback enables targeted correction of both propagated errors and random errors without introducing additional errors, overcoming the limitations of 1+D precoding.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If typical Decision-Feedback Equalizer (DFE) is used to remove post-cursor ISI, then equalization performance is improved, but error propagation is induced

Engineering Contradiction:
Improveequalization performanceVSAvoiderror propagation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary error detection and correction system between the DFE and the final output. The error detection circuit acts as a mediator that identifies errors generated by the DFE's feedback mechanism, and the error correction circuit serves as another intermediary that corrects these errors before they propagate further. This intermediary layer preserves the DFE's equalization benefits while eliminating its harmful error propagation effect.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4250652B1Error detection and correction device capable of detecting head position of suspicious error and performing forward error propagation path tracking for providing information needed by follow-up error correction and associated method
Publication Date: 2026.05.06 MEDIATEK INC
  • EP4250652B1 patent drawingFigure 1
  • EP4250652B1 patent drawingFigure 2
  • EP4250652B1 patent drawingFigure 3

AI summary

An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.