DFE Latch Circuit Baseline Offset for Lower Propagation Delay
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Solution Overview
Problem
Data transceivers in memory devices suffer from significant propagation delays, limiting data transfer rates and efficiency.
Innovation Solution
A latch circuit with a decision feedback equalizer (DFE) that reduces propagation delay by adjusting the baseline voltage using an offset voltage based on previous data bits, allowing for higher clock frequencies and reduced tracking times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional latch circuits are used, then the circuit structure is simple, but the propagation delay is significant which limits data transfer rates
Solution Approach 1:
The latch circuit performs preliminary action by adjusting the baseline voltage to a predicted future voltage level before the actual data arrival. This is achieved by monitoring previous data bits and proactively setting the baseline voltage to compensate for expected inter-symbol interference, thereby reducing the propagation delay when the actual data bit arrives and needs to be processed.
Solution Approach 2:
The latch circuit implements dynamics by making the baseline voltage adjustable and adaptive rather than fixed. The circuit dynamically changes the baseline voltage level based on the sequence of previous data bits, allowing the voltage baseline to adapt to varying signal conditions and minimize propagation delay under different operating conditions.
2Loss of time
If the baseline voltage is adjusted using offset voltage based on previous data bits, then propagation delay is reduced, but the device complexity increases
Solution Approach 1:
The latch circuit applies feedback by monitoring the sequence of previous data bits and using this information to adjust the baseline voltage. The feedback mechanism analyzes past signal patterns and feeds this information back to the voltage adjustment circuitry, which then modifies the baseline voltage to compensate for anticipated inter-symbol interference, reducing propagation delay through intelligent adaptation.
Solution Approach 2:
The circuit implements parameter changes by dynamically modifying the baseline voltage parameter based on detected signal patterns. Instead of using a fixed voltage level, the circuit changes the voltage parameter adaptively according to the sequence of received data bits, allowing optimization of propagation delay through parameter adaptation rather than structural complexity.
3Productivity
If higher clock frequencies are used to increase data transfer rates, then productivity improves, but the propagation delay becomes more significant
Solution Approach 1:
By performing preliminary adjustment of the baseline voltage based on previous data bits, the circuit prepares the voltage baseline in advance before the next data bit arrives. This preliminary action reduces the effective propagation delay, allowing the circuit to operate at higher clock frequencies without sacrificing signal integrity or increasing delay, thereby improving productivity.
Data Source
AI summary
This disclosure is directed to a latch circuit of a decision feedback equalizer (DFE). The latch circuit may sample (e.g., clock-in) each input data bit during a respective sampling time of each latch circuit operation cycle after a reduced propagation delay compared to other latch circuits. The latch circuit may have a reset time and a tracking time before each sampling time that may reduce the propagation delay of each data bit being received during the sampling time. During the track time, the latch circuit may combine (e.g., add, subtract) an offset voltage, generated based on based on one or more previously received data bits and/or characteristics of the latch circuit, with a baseline voltage of the latch circuit. The latch circuit may sense a logic level of each data bit being received during the sampling time based on detecting changes to the baseline voltage combined with the offset voltage.