Decision Feedback Equalizer With Phase-Diverse Clocking
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Solution Overview
Problem
Conventional decision feedback equalizers (DFEs) face limitations in achieving accurate data recovery at high transmission rates due to severe channel distortion, noise amplification, and data bit loss at clock signal transitions, especially when operating with non-standard clock duty cycles.
Innovation Solution
The proposed DFE design incorporates summer circuits, flip-flops, multiplexers, and feedback generators with multiple clock signals having predetermined phase differences, eliminating the need for loop unrolling and ensuring the fundamental timing limit is achieved without data bit loss, even with oscillators that do not guarantee a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If loop unrolling technique is used in half-rate clock architecture, then fundamental timing limit is extended to two UI, but data bit loss occurs at clock signal transitions
Solution Approach 1:
The patent applies preliminary action by performing data preparation and offset voltage application before the critical clock transition point. The flip-flops are designed to complete their state transitions and data latching before the clock signal changes duty cycle, preventing data bit loss at transitions while maintaining the extended timing limit benefit of loop unrolling.
Solution Approach 2:
The patent implements dynamics by using multiple clock signals with different phase relationships (90-degree and 180-degree phase differences) to drive different stages of the equalizer. This dynamic clocking scheme allows the system to adapt to the extended timing requirements of loop unrolling while maintaining synchronized data capture and preventing data loss at transitions.
2Adaptability or versatility
If conventional DFE is implemented with non-standard clock duty cycles, then design flexibility is improved, but data bit loss occurs at clock transitions
Solution Approach 1:
The patent ensures that all data latching and processing operations are completed before the clock signal transitions to a different duty cycle. The flip-flops are positioned and timed to capture data in advance of duty cycle changes, allowing the system to operate with variable clock duty cycles (including non-standard values) without losing data bits during transitions.
Solution Approach 2:
The patent employs feedback mechanisms where the clock signal duty cycle is monitored and the flip-flop operation timing is adjusted accordingly. This feedback ensures that data capture and processing always complete before the next duty cycle transition, maintaining reliability regardless of the specific duty cycle value used.
3Measurement precision
If linear equalizer is used to minimize distortion, then noise amplification occurs in severe channel conditions
Solution Approach 1:
The patent implements a decision feedback equalizer architecture where the equalization process uses feedback from previously detected data bits to compensate for inter-symbol interference. This feedback mechanism allows the system to reduce distortion in severe channel conditions without amplifying noise, as the feedback path provides a noise-free reference from the decision circuit that is used to generate correction signals.
Solution Approach 2:
The patent introduces an intermediate feedback path that mediates between the received distorted signal and the final decision output. The feedback equalizer generates correction signals based on previously detected bits and subtracts predicted interference from the current signal before the decision circuit, effectively removing distortion without amplifying noise in the main signal path.
4Measurement precision
If more taps are added to DFE to correct severe distortion, then equalization performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the equalization function across multiple flip-flops and clock phases, distributing the computational load and tap operations across different time intervals. This segmentation allows the implementation of multiple taps for severe distortion correction while organizing the complexity into manageable, synchronized stages that can be implemented efficiently in hardware.
Solution Approach 2:
The patent uses periodic clock signals with specific phase relationships to drive the sequential operation of multiple flip-flops and tap calculations. By organizing the equalization process into periodic cycles where each phase handles specific tap operations, the system can support multiple taps for improved equalization performance while maintaining regular, predictable timing that simplifies hardware implementation.
Data Source
AI summary
A decision feedback equalizer (DFE) includes first through sixth flip-flops, and first and second summer circuits. The first through fourth flip-flops sample an analog input signal received at the first and second summer circuits, detect the logic level of a data bit in the analog input signal and generate the first through fourth compensated signals. The first multiplexer outputs at least one of the first and second compensated signals as a first feedback signal, based on a fourth feedback signal generated by the sixth flip-flop. The second multiplexer outputs at least one of the third and fourth compensated signals as a second feedback signal, based on a third feedback signal generated by the fifth flip-flop. The first and second feedback signals are multiplied by a weight coefficient and fed back to the first and second summer circuit, respectively, to compensate an error in the analog input signal.