Decision Feedback Equalizer With Phase-Opposed Latches For ISI Correction
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Solution Overview
Problem
Decision feedback equalizers in serial transmission systems face challenges in reducing correction delay and achieving sufficient ISI compensation, particularly due to bandwidth limitations and timing constraints, which can lead to errors in data recovery.
Innovation Solution
The proposed solution involves a decision feedback equalizer architecture that includes a multiplexer controlled by a clock signal to generate digital levels for correction coefficients, paired latches in phase opposition for generating bit replicas, and additional latches for cascaded correction, reducing propagation delay and improving sensitivity for accurate ISI deletion across multiple preceding bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decision feedback equalization is implemented to compensate for channel degradation, then signal recovery accuracy is improved, but correction delay increases
Solution Approach 1:
The equalization process is divided into multiple stages: linear equalization for initial signal restoration, followed by decision feedback equalization for residual ISI removal. This segmentation allows each stage to optimize for its specific function, with the linear equalizer handling amplitude reduction and the DFE handling timing jitter, thereby improving overall accuracy without excessive delay in any single stage.
Solution Approach 2:
The linear equalizer performs preliminary signal restoration before the DFE stage processes the signal. By pre-compensating for channel effects such as amplitude reduction and initial ISI, the preliminary action reduces the burden on the subsequent DFE stage, allowing faster convergence and reduced correction delay while maintaining high signal recovery accuracy.
2Reliability
If linear equalization is used to match the reverse of channel transfer function, then eye aperture is improved, but capability to compensate for high frequency losses is inadequate
Solution Approach 1:
The patent combines linear equalization and decision feedback equalization into a hybrid equalization system. The linear equalizer component matches the reverse of the channel transfer function to improve eye aperture, while the DFE component provides additional compensation for high frequency losses through feedback-based ISI cancellation, achieving both goals simultaneously.
Solution Approach 2:
The equalization system is designed to perform multiple functions: the linear equalizer handles amplitude reduction and initial ISI compensation, while the DFE stage handles residual ISI and high frequency loss compensation. This multi-functional approach allows the system to address both eye aperture improvement and frequency loss compensation within a single unified architecture.
3Measurement precision
If DFE corrects incoming bit based on previous bits, then ISI deletion accuracy is improved, but propagation delay increases
Solution Approach 1:
The DFE implementation uses a limited number of feedback taps (e.g., 3-5 taps) to correct ISI from previous bits, rather than attempting to compensate for all possible previous bits. This partial action approach achieves sufficient ISI deletion accuracy for practical applications while keeping the propagation delay and computational complexity within acceptable limits.
Data Source
AI summary
A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.