Decision Feedback Equalizer Reset for High-Speed Memory Links
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Solution Overview
Problem
As memory device operating speeds increase, there is insufficient time for the Decision Feedback Equalizer (DFE) reset operation to be completed prior to another memory operation, leading to inefficiencies in distortion correction.
Innovation Solution
Implementing a DFE architecture that utilizes double tail latches without reset latches and performs reset operations without direct reset signals, reducing reset operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DFE uses traditional reset architecture with reset latches, then the reset operation can be performed reliably, but the reset operation time becomes too long for high-speed memory operations
Solution Approach 1:
The patent removes reset latches from the DFE architecture, extracting the time-consuming reset operation component. Instead of using traditional reset latches that require clock cycles to clear, the invention uses a simplified reset mechanism that directly resets the equalizer coefficients without the overhead of latch reset operations, thereby reducing reset time while maintaining reliability
Solution Approach 2:
The patent performs preliminary reset of the equalizer coefficients before data processing begins. By pre-initializing the coefficients to known values and using a dedicated reset path that operates independently of the main data path, the system ensures that reset is completed before operational requirements are imposed, eliminating the need for repeated reset operations during high-speed operation
2Productivity
If the memory device operates at higher data rates, then the productivity increases, but the time available for DFE reset operation decreases
Solution Approach 1:
The patent enables continuous equalizer operation by implementing a reset mechanism that does not interrupt the data processing flow. The reset operation is performed in parallel with data reception and processing, allowing the DFE to maintain continuous correction of inter-symbol interference even during reset operations, thus supporting high data rates without loss of productivity
Solution Approach 2:
The patent implements dynamic coefficient adjustment where the equalizer can adapt its coefficients in real-time based on incoming signal conditions. This dynamic adaptation allows the system to quickly converge to optimal settings during operation, reducing the need for lengthy reset periods and enabling the system to keep pace with high data rates
Data Source
AI summary
A device is provided that includes decision feedback equalizer (DFE) reset circuitry. The DFE reset circuitry includes synchronous circuitry and the DFE reset circuitry is configured to receive a DFE reset signal to initiate a reset operation of a DFE, generate a first control signal based upon the DFE reset signal, and transmit the first control signal to alter a data signal generated in a summer circuit of the DFE to affect the reset operation of the DFE.